Capture The Bug Hackathon

Table of Contents

• Introduction
• Level-1 Design-1 Multiplexer
• Level-1 Design-2 Sequence Detector
• Level-2 Design-1 Bitmanipulation Coprocessor
• Level-3 Design-1 Median Filter
• Conclusion
• Author
• Acknowledgements
• References

Introduction

Capture the bug hackathon presented a series of verification challenges wherein the participants had to detect hidden bugs in RTL design code using Vyoma's UpTickPro tool. This documentation presents a brief about each design followed by the tests used to reveal the bugs and the debug code statements suggested to make the designs bug free.

Fig. 1 Vyoma's UpTickPro tool environment

Level-1 Design-1 Multiplexer

The first design was that of a 31:1 multiplexer, with 31 input lines (each 2 bit wide), 5 bit select bus and 1 output line. The block diagram of multiplexer with input and output is presented in Fig. 2. A simple test was used wherein the select signal was incremented from 5'd0 to 5'd30. The input corresponding to select signal was driven with 2'd2 and rest all inputs were driven with 2'd1. The output was tested to assert if was equal to 2'd2 for all select inputs, else the DUT was said to fail the test.

Fig. 2 Multiplexer block diagram

Test Scenario 1

• Test inputs sel = 5'd12, inp12 = 2'd2, inp0-inp30 except inp12 = 2'd1
• Test output out = 2'd0
• Expected output out = 2'd2

Fig. 3 Failed test output

Debug Scenario 1

• Can be traced to line 40, where case(sel) in matched with 5'b01101 instead of 5'b01100

Fig. 4 Buggy code

• Debug Strategy: Replace 5'b01101 with 5'b01100 in line 40

Test Scenario 2

• Test inputs sel = 5'd30, inp30 = 2'd2, inp0-inp29 = 2'd1
• Test output out = 2'd0
• Expected output out = 2'd2

Fig. 5 Failed test output

Debug Scenario 2

• Can be traced to line 58, where case 5'b11110 is missing and case(sel) is matched with default

Fig. 6 Buggy code

• Debug Strategy: Add case 5'b11110 : out = inp30; to line 58 before default case

Level-1 Design-2 Sequence Detector

The second design was that of a 1011 sequence detector that had a serial input inp_bit, reset and clock as its inputs and seq_seen as the output that goes HIGH when the 1011 sequence is detected. The detector was to also detect overlapping sequence i.e. where final bits of a non sequence can be start of another sequence. Eg. 111011 or 101011. A block diagram of DUT with inputs and outputs is presented in Fig. 7, a simple timing diagram is also shown. To test the DUT a random sequence of 0's and 1's was generated and processed using python to produce an expected seq_seen list. The DUT was driven with the test sequence and asserted every clock cycled to check if the expected seq_seen matches simulated seq_seen, else the DUT was said to fail the test.

Fig. 7 Sequence detector block diagram

Test Scenario 1

• Test inputs reset = 1'b1 for one clock cycle followed by inp_bit = [1,1,0,0,1,0,1,0,1,1,0] every subsequent clock
• Test output seq_seen = 1'b0 on last clock cycle
• Expected output seq_seen = 1'b1 on last clock cycle

Fig. 8 Failed test output

Debug Scenario 1

• Can be traced to line 65, if current_state = SEQ_101 and inp_bit = 1'b0, then next_state should be SEQ_10 not IDLE

Fig. 9 Buggy code

• Debug Strategy: Replace next_state = IDLE; with next_state = SEQ_10; in line 65

Test Scenario 2

• Test inputs reset = 1'b1 for one clock cycle followed by inp_bit = [1,1,0,1,1,1] every subsequent clock
• Test output seq_seen = 1'b0 on last clock cycle
• Expected output seq_seen = 1'b1 on last clock cycle

Fig. 10 Failed test output

Debug Scenario 2

• Can be traced to line 49, if current_state = SEQ_1 and inp_bit = 1'b1, then next_state should be SEQ_1 not IDLE

Fig. 11 Buggy code

• Debug Strategy: Replace next_state = IDLE; with next_state = SEQ_1; in line 49

Test Scenario 3

• Test inputs reset = 1'b1 for one clock cycle followed by inp_bit = [1,0,1,1,1,0,1,1,1] every subsequent clock
• Test output seq_seen = 1'b0 on last clock cycle
• Expected output seq_seen = 1'b1 on last clock cycle

Fig. 12 Failed test output

Debug Scenario 3

• Not sure if this is real bug or intended in specification
• Two subsequent sequences 1011 1011 do not raise seq_seen twice but only once.
• Can be traced to line 69, if current_state = SEQ_1011 then next_state is directly set to IDLE disabling the sequence detector for one cycle

Fig. 13 Buggy code

• Debug Strategy: In line 69 replace next_state = IDLE; with

if(inp_bit == 1)
  next_state = SEQ_1;
else
  next_state = IDLE;

Level-2 Design-1 Bitmanipulation Coprocessor

The third design was that of bitmanipulation coprocessor with four primary inputs, three operands mav_putvalue_src1, mav_putvalue_src2, mav_putvalue_src3 each 32 bit wide and one 32 bit instruction bus mav_putvalue_instr. Inside the block the instruction is decoded and the three operands are processed giving a 32 bit output at mav_putvalue. Since the number of possible input combinations is huge 2^(32*4), a constrained testing approach can be followed. Using the heuristic that the most likely bug can be present in instruction decoding or output calculation, all instructions are tested using fixed and limited values of operands. The possible set of instructions in generated using python, the instruction and operands are fed to a bitmanipulation coprocessor model written in python to generate the expected output. The output of DUT simulation is asserted for every valid instruction to be equal to the expected value, else the DUT was said to fail test.

Fig. 14 Bitmanipulation Coprocessor block diagram

Test Scenario 1

• Test inputs mav_putvalue_src1 = 0x1, mav_putvalue_src2 = 0x0, mav_putvalue_src3 = 0x0 and mav_putvalue_instr = 0x40007033
• Test output mav_putvalue = 0x1
• Expected output mav_putvalue = 0x3

Fig. 15 Failed test output

Debug Scenario 1

• Can be traced to line 2661, for the given mav_putvalue_instr = 32'b0100000_rs2_rs1_111_rd_0110011, the expected output is (mav_putvalue_src1 & ~mav_putvalue_src2)<<1, however the code has been written for (mav_putvalue_src1 & mav_putvalue_src2)<<1

Fig. 16 Buggy code

• Debug Strategy: Replace x__h39889 with (mav_putvalue_src1 & ~mav_putvalue_src2)<<1 in line 2661

Level-3 Design-1 Median Filter

The fourth design was that to be chosen by participants. A median filter was chosen for level 3, it had three 32 bit input words to tranfer twelve 8 bit sized pixel values to the core. The output is a 32 bit word that outputs four 8 bit sized pixels after processing with one clock cycle latency. The design was chosen to utilize the advantages of Vyoma's UpTick pro tool over testbenches written in verilog or VHDL. Since the testbench is written in a python environment, the image processing and matrix manipulation modules opencv and numpy can be leveraged to use. An image was fed to median filter in proper format and the output pixels were rearranged to form the filtered image. The resuling image was compared with the output from prebuilt median filter in opencv module. If they did not match then the dut was said to fail the test. A visual test can be created by subtracting dut and software results, for a proper match the output image is full of 0's and is completely black.

Fig. 17 Median filter architecture

Test Scenario 1

• Test input Input image as presented in Fig. 18
• Test output DUT filtered image as presented in Fig. 18
• Expected output Software filtered image as presented in Fig. 18

a) Input image	b) DUT filtered image	c) Software filtered image	d) Difference image

Fig. 18 Failed test output

Debug Scenario 1

To debug the design, a small matrix

[12, 31, 23, 52]
[121, 41, 41, 54]
[54, 1, 63, 41] 

was fed to the core and each submodule in the core was tested separately. The first one was a common network that took in twelve pixels and perfored sort for every three adjacent pixels.

• Test inputs common network input = [41, 54, 52, 63, 41, 23, 1, 41, 31, 54, 121, 12]
• Test output common network output = [52, 54, 41, 23, 41, 63, 31, 41, 1, 12, 121, 54]
• Expected output common network output = [54, 52, 41, 63, 41, 23, 41, 31, 1, 121, 54, 12]

Fig. 19 Failed test output

• Can be traced to line 376 of module node wherein the comparison has been done using data_b - data_a > 0, although this is allowed in software programming languages with large data width, the data widths of pixel is 8 bit wide and subtraction of unsigned numbers is not performed properly resulting in incorrect comparison.

Fig. 20 Buggy code

• Debug Strategy: Replace data_b - data_a > 0 with data_b > data_a in line 376

Conclusion

This repository presents testing and debug results using Vyoma's UpTick pro tool for four RTL designs written in verilog. The hackathon provides a new perspective of testing by leveraging python language and its modules. New image processing and ML related hardware implementations can also be directly tested using this software.

Author

Soumitro Vyapari, B.Tech(EE), Indian Institute of Technology Tirupati, Andhra Pradesh 517506.

Acknowledgements

• Kunal Ghosh, Co-founder, VSD Corp. Pvt Ltd.
• Lavanya J
• Vyoma Systems
• NIELIT
• Hackathon community

References

1. Miguel A. Vega-Rodr´ıguez, Juan Sanchez-P ´ erez, and Juan A. Gomez-Pulido. An fpga-based implementation for median filter meeting the realtime requirements of automated visual inspection systems. 01 2002.
   
2. Wikipedia contributors. Bitonic sorter — Wikipedia, the free encyclopedia, 2022.
   
3. cocotb docs