RegFiles override and override

{
    val raw = io.commit.map{ x => x.raw }
    val phy = io.commit.map{ x => x.phy }
    val idx_pre = io.commit.map{ x => archit_ptr(x.raw) }

    for ( i <- 0 until cmm_chn ) {
      def m = cmm_chn-1-i

      io.commit(m).is_writeback := log(phy(m)) === "b11".U

      when( io.commit(m).is_MisPredict | io.commit(m).is_abort ) {
        /** clear all log to 0, except that archit_ptr point to, may be override */
        for ( j <- 0 until dp-1 ) yield {log_reg(j) := Mux( archit_ptr.exists( (x:UInt) => (x === j.U) ), log(j), "b00".U )}
      }
      when( io.commit(m).is_MisPredict | io.commit(m).is_comfirm ) {
        /** override the log(clear) */
        assert( io.commit(m).is_writeback )
        for ( j <- 0 until dp-1 ) yield {
          when(j.U === idx_pre(m) ) {log_reg(j) := 0.U} // the log, that used before commit, will be clear to 0
        }
        assert( log_reg(phy(m)) === "b11".U, "log_reg which going to commit to will be overrided to \"b11\" if there is an abort in-front." )
        log_reg(phy(m)) := "b11".U //the log, that going to use after commit should keep to be "b11"
      }


      when( io.commit(i).is_MisPredict | io.commit(i).is_comfirm ) {
        archit_ptr(raw(i)) := phy(i)
      }


      when ( io.commit(m).is_MisPredict | io.commit(m).is_abort ) {
        for ( j <- 0 until 32 ) yield {
          rename_ptr(j) := archit_ptr(j)
          for ( n <- 0 until m ) {
            when( j.U === raw(n) & io.commit(n).is_comfirm ) {
              rename_ptr(j) := phy(n) //override renme_ptr when the perivious chn comfirm
            } 
          }
          when( j.U === raw(m) & io.commit(m).is_MisPredict ) { rename_ptr(j) := phy(m) } //override renme_ptr when the this chn is mispredict
        }

      }
    }
  }