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sunxi: add T113-S3 support
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The Allwinner T113-s3 (sun8i) SoC features a dual-core Cortex-A7 ARM CPU and
128MB of DDR3 memory in the same physical package. It supports industrial
temperature ranges. Most of the IP blocks are shared with the D1/D1s core.
There are multiple variants of the SoC, which may vary in the included memory
size, with some of them including a C906 RISC-V co-processor.

Boards supported:
 - MangoPi MQDual T113
   - wireless-only (RTL8723DS)

 - MYIR MYD-YT113 eMMC
   - 1Gbit ethernet (Motorcomm PHY)
   - 4GByte eMMC
   - M.2-type slot for 4G/5G cards, plus 2x SIM slot
   - USB 2.0 ports
   - GPIO/I2C/SPI/CAN ports

 - MYIR MYD-YT113 SPI
   - Same as above but with 256Mbyte flash instead of eMMC

 - Rongpin RP-T113
   - 100Mbit ethernet (ICplus IP101GR PHY)
   - miniPCIe slot for 4G cards, plus 1x SIM slot
   - 3x USB 2.0 ports
   - RTL8723BS wireless
   - HYM8563 RTC
   - GPIO/I2C/SPI/CAN ports

Signed-off-by: Zoltan HERPAI <[email protected]>
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@wigyori
wigyori committed May 27, 2024
1 parent 0a861a0 commit 834f929
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31 changes: 31 additions & 0 deletions package/boot/uboot-sunxi/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -373,7 +373,38 @@ define U-Boot/bananapi_p2_zero
endef


define U-Boot/mangopi_mqdual_t113
BUILD_SUBTARGET:=cortexa7
NAME:=MangoPi MQDual (T113)
BUILD_DEVICES:=widora_mangopi-mqdual-t113
endef

define U-Boot/myir_myd_t113x
BUILD_SUBTARGET:=cortexa7
NAME:=MYIR MYD-T113X
BUILD_DEVICES:=myir_myd-yt113x
UENV:=t113.ttyS5
endef

define U-Boot/myir_myd_t113x-spi
BUILD_SUBTARGET:=cortexa7
NAME:=MYIR MYD-T113X SPI
BUILD_DEVICES:=myir_myd-yt113x-spi
UENV:=t113.ttyS5
endef

define U-Boot/rongpin_rp_t113
BUILD_SUBTARGET:=cortexa7
NAME:=Rongpin RP-T113
BUILD_DEVICES:=rongpin_rp-t113
UENV:=t113.ttyS3
endef

UBOOT_TARGETS := \
mangopi_mqdual_t113 \
myir_myd_t113x \
myir_myd_t113x-spi \
rongpin_rp_t113 \
a64-olinuxino \
a64-olinuxino-emmc \
A10-OLinuXino-Lime \
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75 changes: 75 additions & 0 deletions package/boot/uboot-sunxi/patches/400-sunxi-clock-h6-prepare-for-PRCM-less-SoCs.patch
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@@ -0,0 +1,75 @@
From f26cc77a06a9efb561396adc1c02f01e5c5170c5 Mon Sep 17 00:00:00 2001
From: Andre Przywara <[email protected]>
Date: Fri, 21 Jul 2023 14:45:59 +0100
Subject: [PATCH 4000/4018] sunxi: clock: h6: prepare for PRCM less SoCs

The Allwinner D1/R528/T113 SoCs have a very minimal separate
"management" power plane, with almost no device attached to it (so
no r_i2c or r_uart). This means we don't need to flip any clock gates in
the PRCM block, which in fact those SoCs do not have.

Prepare the code for those SoCs by making the PRCM block optional in the
H6 SPL clock code, which we otherwise share to this new family of SoCs.
If the memory map (cpu.h) does not define the PRCM address, we simply
skip any attempt to program gates there.

Signed-off-by: Andre Przywara <[email protected]>
---
arch/arm/mach-sunxi/clock_sun50i_h6.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index bea91c78bc..0d15d53936 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -4,14 +4,20 @@
#include <asm/arch/clock.h>
#include <asm/arch/prcm.h>

+#ifndef SUNXI_PRCM_BASE
+#define SUNXI_PRCM_BASE 0
+#endif
+
#ifdef CONFIG_SPL_BUILD
-void clock_init_safe(void)
+
+static void clock_init_safe_prcm(void)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_prcm_reg *const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;

+ if (!prcm)
+ return;
+
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) {
/* this seems to enable PLLs on H616 */
setbits_le32(&prcm->sys_pwroff_gating, 0x10);
@@ -30,6 +36,14 @@ void clock_init_safe(void)
/* set PLL VDD LDO output to 1.14 V */
setbits_le32(&prcm->pll_ldo_cfg, 0x60000);
}
+}
+
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ clock_init_safe_prcm();

clock_set_pll1(408000000);

@@ -146,6 +160,8 @@ int clock_twi_onoff(int port, int state)
value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);

if (port == 5) {
+ if (!prcm)
+ return -ENODEV;
shift = 0;
ptr = &prcm->twi_gate_reset;
} else {
--
2.20.1

139 changes: 139 additions & 0 deletions package/boot/uboot-sunxi/patches/401-net-add-ICPlus-PHY-driver.patch
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@@ -0,0 +1,139 @@
From 13339996e5ffd1cf9e276e6403aa14948f27c56a Mon Sep 17 00:00:00 2001
From: Yegor Yefremov <[email protected]>
Date: Wed, 28 Nov 2012 11:15:18 +0100
Subject: [PATCH 4001/4018] net: add ICPlus PHY driver

The driver code was taken from Linux kernel source:
drivers/net/phy/icplus.c

Signed-off-by: Zoltan HERPAI <[email protected]>
Signed-off-by: Yegor Yefremov <[email protected]>
---
drivers/net/phy/Kconfig | 3 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/icplus.c | 87 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 91 insertions(+)
create mode 100644 drivers/net/phy/icplus.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 3d96938eab..afcd1d09c7 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -168,6 +168,9 @@ config PHY_DAVICOM
config PHY_ET1011C
bool "LSI TruePHY ET1011C support"

+config PHY_ICPLUS
+ bool "IC+ IP101 Ethernet PHY support"
+
config PHY_LXT
bool "LXT971 Ethernet PHY support"

diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 2487f366e1..ff7bc1a4f1 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_PHY_CORTINA) += cortina.o
obj-$(CONFIG_PHY_CORTINA_ACCESS) += ca_phy.o
obj-$(CONFIG_PHY_DAVICOM) += davicom.o
obj-$(CONFIG_PHY_ET1011C) += et1011c.o
+obj-$(CONFIG_PHY_ICPLUS) += icplus.o
obj-$(CONFIG_PHY_LXT) += lxt.o
obj-$(CONFIG_PHY_MARVELL) += marvell.o
obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
new file mode 100644
index 0000000000..27a8fbae50
--- /dev/null
+++ b/drivers/net/phy/icplus.c
@@ -0,0 +1,87 @@
+/*
+ * ICPlus PHY drivers
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
+ *
+ */
+#include <phy.h>
+
+/* IP101A/G - IP1001 */
+#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
+#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
+#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
+#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
+#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
+#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
+#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
+#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
+
+static int ip1001_config(struct phy_device *phydev)
+{
+ int c;
+
+ /* Enable Auto Power Saving mode */
+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
+ if (c < 0)
+ return c;
+ c |= IP1001_APS_ON;
+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
+ if (c < 0)
+ return c;
+
+ /* INTR pin used: speed/link/duplex will cause an interrupt */
+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
+ IP101A_G_IRQ_DEFAULT);
+ if (c < 0)
+ return c;
+
+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
+ /*
+ * Additional delay (2ns) used to adjust RX clock phase
+ * at RGMII interface
+ */
+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
+ if (c < 0)
+ return c;
+
+ c |= IP1001_PHASE_SEL_MASK;
+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
+ c);
+ if (c < 0)
+ return c;
+ }
+
+ return 0;
+}
+
+static int ip1001_startup(struct phy_device *phydev)
+{
+ genphy_update_link(phydev);
+ genphy_parse_link(phydev);
+
+ return 0;
+}
+U_BOOT_PHY_DRIVER(lxt971) = {
+ .name = "ICPlus IP1001",
+ .uid = 0x02430d90,
+ .mask = 0x0ffffff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = &ip1001_config,
+ .startup = &ip1001_startup,
+ .shutdown = &genphy_shutdown,
+};
--
2.20.1

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