Computer Organization Project

Table of Contents

• About the Project
• Contents

About The Project

Verilog code simulation of 李毅郎 Computer Organization Course at National Chiao Tung University(NCTU).

Contents

Programming Language: Verilog

Lab0 Design a simple marquee

Lab1 Implement a 32-bit ALU

Lab2 Implement a simple single cycle CPU

Lab3 Modify CPU in Lab 2 to support R-type, I-type and jump instruction

Lab4 Implement a simple version pipelined CPU nased on Lab 3

Lab5 Implement an advanced version pipelined CPU based on Lab 4

Lab6 Cache Stimulator