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1. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   C++

2. common_cells common_cells Public

   Forked from pulp-platform/common_cells

   Common SystemVerilog components

   SystemVerilog

3. fpnew fpnew Public

   Forked from openhwgroup/cvfpu

   Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

   SystemVerilog

4. riscv-dbg riscv-dbg Public

   Forked from pulp-platform/riscv-dbg

   RISC-V Debug Support for our PULP RISC-V Cores

   SystemVerilog

5. axi axi Public

   Forked from pulp-platform/axi

   AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

   SystemVerilog

6. axi_slice axi_slice Public

   Forked from pulp-platform/axi_slice

   Pipelines the AXI path with FIFOs

   SystemVerilog