Merge branch 'acidanthera:master' into YamingNetwork

wy414012 · Nov 17, 2024 · cea93a9 · cea93a9
2 parents d704217 + 1493b56
commit cea93a9
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diff --git a/Changelog.md b/Changelog.md
@@ -3,6 +3,8 @@ OpenCore Changelog
 #### v1.0.3
 - Fixed support for `AMD_CPU_EXT_FAMILY_1AH`, thx @Shaneee
 - Fixed EHCI handoff logic in OpenDuet, causing older machines to hang at start
+- Added Arrow Lake CPU detection
+- Fixed Raptor Lake CPU detection
 
 #### v1.0.2
 - Fixed error in macrecovery when running headless, thx @mkorje

diff --git a/Include/Acidanthera/Library/OcCpuLib.h b/Include/Acidanthera/Library/OcCpuLib.h
@@ -56,6 +56,8 @@ typedef enum {
   OcCpuGenerationIceLake,
   OcCpuGenerationTigerLake,
   OcCpuGenerationAlderLake,
+  OcCpuGenerationRaptorLake,
+  OcCpuGenerationArrowLake,
   OcCpuGenerationMaxGeneration
 } OC_CPU_GENERATION;
 

diff --git a/Include/Intel/IndustryStandard/ProcessorInfo.h b/Include/Intel/IndustryStandard/ProcessorInfo.h
@@ -250,6 +250,9 @@ typedef enum {
 #define CPU_MODEL_ALDERLAKE_S     0x97
 #define CPU_MODEL_RAPTORLAKE_S    0xB7 ///< Raptor Lake B0 stepping
 #define CPU_MODEL_RAPTORLAKE_HX   0xBF ///< Raptor Lake C0 stepping
+#define CPU_MODEL_ARROWLAKE_S     0xC6 ///< desktop ArrowLake
+#define CPU_MODEL_ARROWLAKE_HX    0xC5
+#define CPU_MODEL_ARROWLAKE_U     0xB5
 
 #define AMD_CPU_FAMILY          0xF
 #define AMD_CPU_EXT_FAMILY_0FH  0x0

diff --git a/Library/OcCpuLib/AppleCpuSupport.c b/Library/OcCpuLib/AppleCpuSupport.c
@@ -613,6 +613,9 @@ InternalDetectAppleProcessorType (
     case CPU_MODEL_ALDERLAKE_S:    // 0x97 FIXME - unknown, for now
     case CPU_MODEL_RAPTORLAKE_S:   // 0xB7 FIXME - unknown, for now
     case CPU_MODEL_RAPTORLAKE_HX:  // 0xBF FIXME - unknown, for now
+    case CPU_MODEL_ARROWLAKE_S:    // 0xC6 FIXME - unknown, for now
+    case CPU_MODEL_ARROWLAKE_HX:   // 0xC5 FIXME - unknown, for now
+    case CPU_MODEL_ARROWLAKE_U:    // 0xB5 FIXME - unknown, for now
       if (AppleMajorType == AppleProcessorMajorM3) {
         // MB101 (m3 7Y32)
         return AppleProcessorTypeCoreM3Type7; // 0x0C07

diff --git a/Library/OcCpuLib/OcCpuLib.c b/Library/OcCpuLib/OcCpuLib.c
@@ -1491,6 +1491,15 @@ InternalDetectIntelProcessorGeneration (
       case CPU_MODEL_ALDERLAKE_S:
         CpuGeneration = OcCpuGenerationAlderLake;
         break;
+      case CPU_MODEL_RAPTORLAKE_S:
+      case CPU_MODEL_RAPTORLAKE_HX:
+        CpuGeneration = OcCpuGenerationRaptorLake;
+        break;
+      case CPU_MODEL_ARROWLAKE_S:
+      case CPU_MODEL_ARROWLAKE_HX:
+      case CPU_MODEL_ARROWLAKE_U:
+        CpuGeneration = OcCpuGenerationArrowLake;
+        break;
       default:
         if (CpuInfo->Model < CPU_MODEL_PENRYN) {
           CpuGeneration = OcCpuGenerationPreYonah;