Bare Metal Network Example

*** WIP ***

Original Article: https://www.programmersought.com/article/78153940676/

• Open Vivado
• Select new Project
  • RTL Project
  • Do not specify sources at this time
• Select part xc7z010clg400-1
• Select Finish

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• Select Create Block design from the Flow Navigator Panel under IP Integrator (on the left)
• Press OK
• Select the + in middle of the Diagram window
• Search for ZYNQ and select ZYNQ7 Processing System
• Double click on the newly created Block to open the re-customize IP dialog
  • Select clock configuration

Component	Clock Source	REq Freq
Processor/Memory Clocks
CPU	ARM PLL	666.666666
DDR	DDR PLL	533.333333
IO Periphal Clocks
SMC	IO PLL	100
ENET0		100 Mbps
SDIO	IO PLL	100
PL Fabric Clocks
[x] FCLK_CLK0	IO PLL	100

• Select DDR Configuration

Name	Select
DDR Controller Configuratio
Memory Type	DDR 3
Memory Part	MT41K
Effective DRAM Bus Width	16 Bit
ECC	Disabled
Burst Length	8
DDR	533.333333
Internal VRef	[]
Juntion Temperature	Normal

• Select MIO Configuration
  • ENET0 - EMIO
  • SD0 - MIO 40 .. 45
  • UART1 - MIO 24 .. 25

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Go back to the Block Design window and start connecting. What needs to be noted here is that ZYNQ defaults to the Gigabit Ethernet port GMII, and the board has a 100M interface, so you need to use the Concat module to convert it in the middle

TODO: Generate new Image will use one from original article for now also explain how to do this (what to click etc)

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