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RISCV: remove the direct-vectoring & interrupt-preemption feature…
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…s and enable them by default (esp-rs#1310)

* Remove the `direct-vectoring` feature

* Enables the feature by default
* renames the old direct_vectoring enable function `enable_direct`

* Make enable_direct safe, move it out of vectored module

* enable interrupt preemption by default for riscv

* remove pub from cpu intr handlers

* add enable_direct for Xtensa too

* Fix flip-link feature

* Fix up interrupt docs

* changelog

* fix clippy suggestions

* Disable P4 workflow
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MabezDev authored and yanshay committed Mar 25, 2024
1 parent 828d91c commit 5bffa28
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Showing 6 changed files with 59 additions and 36 deletions.
1 change: 1 addition & 0 deletions esp-hal/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- `Delay::delay(time: fugit::MicrosDurationU64)`
- Added async support for TWAI (#1320)
- Add TWAI support for ESP32-C6 (#1323)
- `interrupt::enable` now has a direct CPU enable counter part, `interrupt::enable_direct` (#1310)

### Fixed

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2 changes: 2 additions & 0 deletions esp-hal/Cargo.toml
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Expand Up @@ -137,6 +137,8 @@ esp32s3 = ["dep:esp32s3", "xtensa", "procmacros/has-ulp-core", "xtensa-lx/spin",
## Move the stack to start of RAM to get zero-cost stack overflow protection
## (ESP32-C6 and ESPS32-H2 only!).
flip-link = ["esp-riscv-rt/fix-sp"]
## Configuration for placing device drivers in the IRAM for faster access.
place-spi-driver-in-ram = []
## Initialize the `.data` section of memory.
rv-init-data = ["esp-riscv-rt?/init-data", "esp-riscv-rt?/init-rw-text"]
## Zero the `.bss` section of low-power memory.
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38 changes: 37 additions & 1 deletion esp-hal/build.rs
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Expand Up @@ -7,9 +7,45 @@ use std::{
str::FromStr,
};

use esp_build::assert_unique_used_features;
use esp_metadata::{Chip, Config};

// Macros taken from:
// https://github.com/TheDan64/inkwell/blob/36c3b10/src/lib.rs#L81-L110

// Given some features, assert that AT MOST one of the features is enabled.
macro_rules! assert_unique_features {
() => {};

( $first:tt $(,$rest:tt)* ) => {
$(
#[cfg(all(feature = $first, feature = $rest))]
compile_error!(concat!("Features \"", $first, "\" and \"", $rest, "\" cannot be used together"));
)*
assert_unique_features!($($rest),*);
};
}

// Given some features, assert that AT LEAST one of the features is enabled.
macro_rules! assert_used_features {
( $all:tt ) => {
#[cfg(not(feature = $all))]
compile_error!(concat!("The feature flag must be provided: ", $all));
};

( $($all:tt),+ ) => {
#[cfg(not(any($(feature = $all),*)))]
compile_error!(concat!("One of the feature flags must be provided: ", $($all, ", "),*));
};
}

// Given some features, assert that EXACTLY one of the features is enabled.
macro_rules! assert_unique_used_features {
( $($all:tt),* ) => {
assert_unique_features!($($all),*);
assert_used_features!($($all),*);
}
}

fn main() -> Result<(), Box<dyn Error>> {
// NOTE: update when adding new device support!
// Ensure that exactly one chip has been specified:
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38 changes: 19 additions & 19 deletions esp-hal/src/interrupt/riscv.rs
Original file line number Diff line number Diff line change
Expand Up @@ -440,119 +440,119 @@ mod vectored {

#[no_mangle]
#[ram]
unsafe fn interrupt1(context: &mut TrapFrame) {
unsafe fn cpu_int_1_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt1, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt2(context: &mut TrapFrame) {
unsafe fn cpu_int_2_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt2, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt3(context: &mut TrapFrame) {
unsafe fn cpu_int_3_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt3, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt4(context: &mut TrapFrame) {
unsafe fn cpu_int_4_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt4, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt5(context: &mut TrapFrame) {
unsafe fn cpu_int_5_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt5, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt6(context: &mut TrapFrame) {
unsafe fn cpu_int_6_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt6, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt7(context: &mut TrapFrame) {
unsafe fn cpu_int_7_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt7, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt8(context: &mut TrapFrame) {
unsafe fn cpu_int_8_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt8, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt9(context: &mut TrapFrame) {
unsafe fn cpu_int_9_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt9, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt10(context: &mut TrapFrame) {
unsafe fn cpu_int_10_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt10, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt11(context: &mut TrapFrame) {
unsafe fn cpu_int_11_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt11, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt12(context: &mut TrapFrame) {
unsafe fn cpu_int_12_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt12, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt13(context: &mut TrapFrame) {
unsafe fn cpu_int_13_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt13, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt14(context: &mut TrapFrame) {
unsafe fn cpu_int_14_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt14, context)
}

#[no_mangle]
#[ram]
unsafe fn interrupt15(context: &mut TrapFrame) {
unsafe fn cpu_int_15_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt15, context)
}

#[cfg(plic)]
#[no_mangle]
#[ram]
unsafe fn interrupt16(context: &mut TrapFrame) {
unsafe fn cpu_int_16_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt16, context)
}

#[cfg(plic)]
#[no_mangle]
#[ram]
unsafe fn interrupt17(context: &mut TrapFrame) {
unsafe fn cpu_int_17_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt17, context)
}

#[cfg(plic)]
#[no_mangle]
#[ram]
unsafe fn interrupt18(context: &mut TrapFrame) {
unsafe fn cpu_int_18_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt18, context)
}

#[cfg(plic)]
#[no_mangle]
#[ram]
unsafe fn interrupt19(context: &mut TrapFrame) {
unsafe fn cpu_int_19_handler(context: &mut TrapFrame) {
handle_interrupts(CpuInterrupt::Interrupt19, context)
}
}
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15 changes: 0 additions & 15 deletions esp-hal/src/interrupt/xtensa.rs
Original file line number Diff line number Diff line change
Expand Up @@ -68,21 +68,6 @@ pub const RESERVED_INTERRUPTS: &[usize] = &[
CpuInterrupt::Interrupt22EdgePriority3 as _,
];

pub(crate) fn setup_interrupts() {
// disable all known interrupts
// at least after the 2nd stage bootloader there are some interrupts enabled
// (e.g. UART)
for peripheral_interrupt in 0..255 {
crate::soc::peripherals::Interrupt::try_from(peripheral_interrupt)
.map(|intr| {
#[cfg(multi_core)]
disable(Cpu::AppCpu, intr);
disable(Cpu::ProCpu, intr);
})
.ok();
}
}

/// Enable an interrupt by directly binding it to a available CPU interrupt
///
/// Unless you are sure, you most likely want to use [`enable`] with the
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1 change: 0 additions & 1 deletion examples/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,6 @@ esp-backtrace = { version = "0.11.1", features = ["exception-handler", "pa
esp-hal = { version = "0.16.0", path = "../esp-hal", features = ["log"] }
esp-hal-smartled = { version = "0.9.0", path = "../esp-hal-smartled", optional = true }
esp-println = { version = "0.9.1", features = ["log"] }
fugit = "0.3.7"
heapless = "0.8.0"
hex-literal = "0.4.1"
hmac = { version = "0.12.1", default-features = false }
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