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Finish changing march from rv32imac to rv32i
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yhzhang0128 committed May 11, 2022
1 parent b2f596b commit 9d5b0e1
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2 changes: 1 addition & 1 deletion grass/scheduler.c
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Expand Up @@ -35,7 +35,7 @@ void intr_entry(int id) {
if (curr_pid >= GPID_USER_START && earth->tty_intr()) {
/* User process killed by ctrl+c interrupt */
INFO("process %d killed by interrupt", curr_pid);
__asm__ volatile("csrw mepc, %0" ::"r"(0x8005006));
__asm__ volatile("csrw mepc, %0" ::"r"(0x8005008));
return;
}

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4 changes: 2 additions & 2 deletions references/README.md
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Expand Up @@ -47,8 +47,8 @@ The complete memory layout is described in Chapter 4 of the [FE310 manual](sifiv

| Base | Top | Attributes | Description | Notes |
|-------------|-------------|------------|-------------------|------------------------------------------------------------|
| 0x0800_0000 | 0x0800_2FFF | RWX A | ITIM, 12KB | Earth layer bss, data and heap |
| 0x0800_3000 | 0x0800_4FFF | RWX A | ITIM, 8KB | Grass layer code, bss, data and heap |
| 0x0800_0000 | 0x0800_27FF | RWX A | ITIM, 10KB | Earth layer bss, data and heap |
| 0x0800_2800 | 0x0800_4FFF | RWX A | ITIM, 10KB | Grass layer code, bss, data and heap |
| 0x0800_5000 | 0x0800_7FFF | RWX A | ITIM, 12KB | App layer code, bss, data and heap |
| ...... | ...... | ...... | ...... | |
| 0x2000_0000 | 0x203F_FFFF | R XC | Flash ROM, 4MB | FPGA binary of the FE310 RISC-V processor |
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