chisel2verilog

Files for building a docker image that convert chisel source to SystemVerilog. Recommanded way to use this image is convert to apptainer sif image, then run with apptainer.

build

A Nix environment with flake support is necessary, use below command to build the image:

nix build

After success build, a symlink ‘result’ will be created, which linked to actual tar.gz file that can be load with podman load

convertion

Need podman to convert image to apptainer acceptable format.

podman load -i result
podman save localhost/chisel:v0.4 -o tmp.tar.gz
podman image rm localhost/chisel:v0.4

apptainer pull chisel2verilog_5-0.4.sif docker-archive:tmp.tar.gz
rm tmp.tar.gz

usage

Below scala code is placed in example/src directory, with name cnt.scala

package test

import chisel3._

class Cnt extends Module {
  override val desiredName = "cnt"

  val io = IO(new Bundle {
    val inc = Input(Bool())
    val clr = Input(Bool())
    val cnt = Output(UInt(8.W))
  })

  val cntReg = RegInit(0.U(8.W))

  when (io.inc) {
    cntReg := cntReg + 1.U
  }

  when (io.clr) {
    cntReg := 0.U
  }

  io.cnt := cntReg
}

Then with below command, test.Cnt module will convert to cnt.sv in rtl directory.

cd example
mkdir -p rtl

../chisel2verilog_5-0.4.sif src/*.scala -- test.Cnt -td rtl

# or strip debug info with below command
../chisel2verilog_5-0.4.sif src/*.scala -- test.Cnt -td rtl -- --strip-debug-info