lib/stm32: update stm32wb to cube version V1.18.0

Update Cube version for STM32WBxx series on https://github.com/STMicroelectronics from version v1.17.0 to version v1.18.0 Signed-off-by: Abderrahmane Jarmouni <[email protected]>
zephyrproject-rtos · Dec 5, 2023 · 4211cbe · 4211cbe
1 parent 9221c15
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diff --git a/lib/stm32wb/hci/README b/lib/stm32wb/hci/README
@@ -6,7 +6,7 @@ Origin:
    https://github.com/STMicroelectronics/STM32CubeWB
 
 Status:
-   version v1.17.0
+   version v1.18.0
 
 Purpose:
    This library is used on stm32wb series to enable HCI communication between
@@ -48,7 +48,7 @@ URL:
    https://github.com/STMicroelectronics/STM32CubeWB
 
 Commit:
-   d23878380596ba031e33fcfa4841ff91aa1ab024
+   82988c4a028fbc63d85fb44b813535c290f71822
 
 Maintained-by:
    External
@@ -86,4 +86,4 @@ Patch List:
             used as, in Zephyr context, it is  running on C-M4 side.
           Impacted file: app_conf.h
 
-	* Remove trailing whitespaces
+	* Remove trailing whitespaces
diff --git a/lib/stm32wb/hci/app_conf.h b/lib/stm32wb/hci/app_conf.h
@@ -132,14 +132,14 @@
 #define BLE_APPEARANCE_HID_MOUSE                (962)
 
 /**
-*   Identity root key used to derive LTK and CSRK
+*   Identity root key used to derive IRK and DHK(Legacy)
 */
-#define CFG_BLE_IRK     {0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0, 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0}
+#define CFG_BLE_IR     {0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0, 0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC, 0xDE, 0xF0}
 
 /**
-* Encryption root key used to derive LTK and CSRK
+* Encryption root key used to derive LTK(Legacy) and CSRK
 */
-#define CFG_BLE_ERK     {0xFE, 0xDC, 0xBA, 0x09, 0x87, 0x65, 0x43, 0x21, 0xFE, 0xDC, 0xBA, 0x09, 0x87, 0x65, 0x43, 0x21}
+#define CFG_BLE_ER     {0xFE, 0xDC, 0xBA, 0x09, 0x87, 0x65, 0x43, 0x21, 0xFE, 0xDC, 0xBA, 0x09, 0x87, 0x65, 0x43, 0x21}
 
 /**
  * SMPS supply
@@ -219,12 +219,12 @@
 #define CFG_BLE_DATA_LENGTH_EXTENSION   1
 
 /**
- * Sleep clock accuracy in Slave mode (ppm value)
+ * Sleep clock accuracy in Peripheral mode (ppm value)
  */
-#define CFG_BLE_SLAVE_SCA   500
+#define CFG_BLE_PERIPHERAL_SCA   500
 
 /**
- * Sleep clock accuracy in Master mode
+ * Sleep clock accuracy in Central mode
  * 0 : 251 ppm to 500 ppm
  * 1 : 151 ppm to 250 ppm
  * 2 : 101 ppm to 150 ppm
@@ -234,7 +234,7 @@
  * 6 : 21 ppm to 30 ppm
  * 7 : 0 ppm to 20 ppm
  */
-#define CFG_BLE_MASTER_SCA   0
+#define CFG_BLE_CENTRAL_SCA   0
 
 /**
  * LsSource
@@ -255,7 +255,7 @@
 #define CFG_BLE_HSE_STARTUP_TIME  0x148
 
 /**
- * Maximum duration of the connection event when the device is in Slave mode in units of 625/256 us (~2.44 us)
+ * Maximum duration of the connection event when the device is in Peripheral mode in units of 625/256 us (~2.44 us)
  */
 #define CFG_BLE_MAX_CONN_EVENT_LENGTH  (0xFFFFFFFF)
 
@@ -372,10 +372,11 @@
   /* BLE core version (16-bit signed integer).
    * - SHCI_C2_BLE_INIT_BLE_CORE_5_2
    * - SHCI_C2_BLE_INIT_BLE_CORE_5_3
-   * which are used to set: 11(5.2), 12(5.3).
+   * - SHCI_C2_BLE_INIT_BLE_CORE_5_4
+   * which are used to set: 11(5.2), 12(5.3), 13(5.4).
    */
 
-#define CFG_BLE_CORE_VERSION   (SHCI_C2_BLE_INIT_BLE_CORE_5_3)
+#define CFG_BLE_CORE_VERSION   (SHCI_C2_BLE_INIT_BLE_CORE_5_4)
 
 
 /******************************************************************************
@@ -543,8 +544,8 @@ typedef enum
  * Debug
  ******************************************************************************/
 /**
- * When set, this resets some hw resources to set the device in the same state than the power up
- * The FW resets only register that may prevent the FW to run properly
+ * When set, this resets some hw resources to put the device in the same state as at power up.
+ * It resets only register that may prevent the FW to run properly.
  *
  * This shall be set to 0 in a final product
  *

diff --git a/lib/stm32wb/hci/shci.c b/lib/stm32wb/hci/shci.c
@@ -644,6 +644,26 @@ SHCI_CmdStatus_t SHCI_C2_802_15_4_DeInit( void )
   return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
 }
 
+SHCI_CmdStatus_t SHCI_C2_SetSystemClock( SHCI_C2_SET_SYSTEM_CLOCK_Cmd_Param_t clockSel )
+{
+  /**
+   * Buffer is large enough to hold command complete without payload
+   */
+  uint8_t local_buffer[TL_BLEEVT_CC_BUFFER_SIZE];
+  TL_EvtPacket_t * p_rsp;
+
+  p_rsp = (TL_EvtPacket_t *)local_buffer;
+
+  local_buffer[0] = (uint8_t)clockSel;
+
+  shci_send( SHCI_OPCODE_C2_SET_SYSTEM_CLOCK,
+             1,
+             local_buffer,
+             p_rsp );
+
+  return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
+}
+
 /**
  *  Local System COMMAND
  *  These commands are NOT sent to the CPU2

diff --git a/lib/stm32wb/hci/shci.h b/lib/stm32wb/hci/shci.h
@@ -227,6 +227,7 @@ extern "C" {
     SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME,
     SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION,
     SHCI_OCF_C2_802_15_4_DEINIT,
+    SHCI_OCF_C2_SET_SYSTEM_CLOCK,
   } SHCI_OCF_t;
 
 #define SHCI_OPCODE_C2_FUS_GET_STATE         (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE)
@@ -436,7 +437,7 @@ extern "C" {
    * PrWriteListSize
    * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure )
    *
-   * Maximum number of supported prepare write request
+   * Maximum number of supported "prepare write request"
    *    - Min value: given by the macro DEFAULT_PREP_WRITE_LIST_SIZE
    *    - Max value: a value higher than the minimum required can be specified, but it is not recommended
    */
@@ -464,20 +465,20 @@ extern "C" {
   uint16_t AttMtu;
 
   /**
-   * SlaveSca
-   * The sleep clock accuracy (ppm value) that used in BLE connected slave mode to calculate the window widening
+   * PeripheralSca
+   * The sleep clock accuracy (ppm value) that used in BLE connected Peripheral mode to calculate the window widening
    * (in combination with the sleep clock accuracy sent by master in CONNECT_REQ PDU),
    * refer to BLE 5.0 specifications - Vol 6 - Part B - chap 4.5.7 and 4.2.2
    *     - Min value: 0
    *     - Max value: 500 (worst possible admitted by specification)
    */
-  uint16_t SlaveSca;
+  uint16_t PeripheralSca;
 
   /**
-   * MasterSca
-   * The sleep clock accuracy handled in master mode. It is used to determine the connection and advertising events timing.
+   * CentralSca
+   * The sleep clock accuracy handled in Central mode. It is used to determine the connection and advertising events timing.
    * It is transmitted to the slave in CONNEC_REQ PDU used by the slave to calculate the window widening,
-   * see SlaveSca and Bluetooth Core Specification v5.0 Vol 6 - Part B - chap 4.5.7 and 4.2.2
+   * see PeripheralSca and Bluetooth Core Specification v5.0 Vol 6 - Part B - chap 4.5.7 and 4.2.2
    * Possible values:
    *    - 251 ppm to 500 ppm: 0
    *    - 151 ppm to 250 ppm: 1
@@ -488,7 +489,7 @@ extern "C" {
    *    - 21 ppm to 30 ppm: 6
    *    - 0 ppm to 20 ppm: 7
    */
-  uint8_t MasterSca;
+  uint8_t CentralSca;
 
   /**
    * LsSource
@@ -503,7 +504,7 @@ extern "C" {
    * MaxConnEventLength
    * This parameter determines the maximum duration of a slave connection event. When this duration is reached the slave closes
    * the current connections event (whatever is the CE_length parameter specified by the master in HCI_CREATE_CONNECTION HCI command),
-   * expressed in units of 625/256 µs (~2.44 µs)
+   * expressed in units of 625/256 us (~2.44 us)
    *    - Min value: 0 (if 0 is specified, the master and slave perform only a single TX-RX exchange per connection event)
    *    - Max value: 1638400 (4000 ms). A higher value can be specified (max 0xFFFFFFFF) but results in a maximum connection time
    *      of 4000 ms as specified. In this case the parameter is not applied, and the predicted CE length calculated on slave is not shortened
@@ -512,7 +513,7 @@ extern "C" {
 
   /**
    * HsStartupTime
-   * Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 µs (~2.44 µs).
+   * Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 us (~2.44 us).
    *    - Min value: 0
    *    - Max value:  820 (~2 ms). A higher value can be specified, but the value that implemented in stack is forced to ~2 ms
    */
@@ -598,7 +599,7 @@ extern "C" {
   int16_t rx_path_compens;
 
   /* BLE core specification version (8-bit unsigned integer).
-   * values as: 11(5.2), 12(5.3)
+   * values as: 11(5.2), 12(5.3), 13(5.4)
    */
   uint8_t ble_core_version;
 
@@ -829,6 +830,7 @@ extern "C" {
     /** No response parameters*/
 
 #define SHCI_OPCODE_C2_CONFIG   (( SHCI_OGF << 10) + SHCI_OCF_C2_CONFIG)
+
   /** Command parameters */
     typedef PACKED_STRUCT{
       uint8_t PayloadCmdSize;
@@ -843,6 +845,15 @@ extern "C" {
 
 #define SHCI_OPCODE_C2_802_15_4_DEINIT    (( SHCI_OGF << 10) + SHCI_OCF_C2_802_15_4_DEINIT)
 
+#define SHCI_OPCODE_C2_SET_SYSTEM_CLOCK   (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_SYSTEM_CLOCK)
+  /** Command parameters */
+    typedef enum
+    {
+      SET_SYSTEM_CLOCK_HSE_TO_PLL,
+      SET_SYSTEM_CLOCK_PLL_ON_TO_HSE,
+      SET_SYSTEM_CLOCK_PLL_OFF_TO_HSE,
+    }SHCI_C2_SET_SYSTEM_CLOCK_Cmd_Param_t;
+
 /**
  * PayloadCmdSize
  * Value that shall be used
@@ -859,8 +870,8 @@ extern "C" {
 /**
  * Device ID
  */
-#define SHCI_C2_CONFIG_STM32WB55xx                   (0x495)
-#define SHCI_C2_CONFIG_STM32WB15xx                   (0x494)
+#define SHCI_C2_CONFIG_STM32WB55xx                    (0x495)
+#define SHCI_C2_CONFIG_STM32WB15xx                    (0x494)
 
 /**
  * Config1
@@ -878,7 +889,7 @@ extern "C" {
  */
 #define SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE               (1<<0)
 #define SHCI_C2_CONFIG_EVTMASK1_BIT1_BLE_NVM_RAM_UPDATE_ENABLE        (1<<1)
-#define SHCI_C2_CONFIG_EVTMASK1_BIT2_THREAD_NVM_RAM_UPDATE_ENABLE         (1<<2)
+#define SHCI_C2_CONFIG_EVTMASK1_BIT2_THREAD_NVM_RAM_UPDATE_ENABLE     (1<<2)
 #define SHCI_C2_CONFIG_EVTMASK1_BIT3_NVM_START_WRITE_ENABLE           (1<<3)
 #define SHCI_C2_CONFIG_EVTMASK1_BIT4_NVM_END_WRITE_ENABLE             (1<<4)
 #define SHCI_C2_CONFIG_EVTMASK1_BIT5_NVM_START_ERASE_ENABLE           (1<<5)
@@ -965,7 +976,8 @@ extern "C" {
 #define INFO_STACK_TYPE_ZIGBEE_RFD                  0x31
 #define INFO_STACK_TYPE_MAC                         0x40
 #define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC       0x50
-#define INFO_STACK_TYPE_BLE_THREAD_FTD_DYAMIC       0x51
+#define INFO_STACK_TYPE_BLE_THREAD_FTD_DYNAMIC      0x51
+#define INFO_STACK_TYPE_BLE_THREAD_LIGHT_DYNAMIC    0x52
 #define INFO_STACK_TYPE_802154_LLD_TESTS            0x60
 #define INFO_STACK_TYPE_802154_PHY_VALID            0x61
 #define INFO_STACK_TYPE_BLE_PHY_VALID               0x62
@@ -1364,9 +1376,24 @@ typedef struct {
    */
   SHCI_CmdStatus_t SHCI_C2_802_15_4_DeInit( void );
 
-  #ifdef __cplusplus
+  /**
+  * SHCI_C2_SetSystemClock
+  * @brief Request CPU2 to change system clock
+  *
+  * @param clockSel: It can be one of the following list
+  *                -  SET_SYSTEM_CLOCK_HSE_TO_PLL : CPU2 set system clock to PLL, PLL must be configured and started before.
+  *                -  SET_SYSTEM_CLOCK_PLL_ON_TO_HSE : CPU2 set System clock to HSE, PLL is still ON after command execution.
+  *                -  SET_SYSTEM_CLOCK_PLL_OFF_TO_HSE : CPU2 set System clock to HSE, PLL is turned OFF after command execution.
+  *
+  * @retval Status
+  */
+  SHCI_CmdStatus_t SHCI_C2_SetSystemClock( SHCI_C2_SET_SYSTEM_CLOCK_Cmd_Param_t clockSel );
+
+
+#ifdef __cplusplus
 }
 #endif
 
 #endif /*__SHCI_H */
 
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/