devicetree: Add grove connector definition for m5stack_core2

Basic pinout definition. Signed-off-by: Martin Kiepfer <[email protected]>
zephyrproject-rtos · Sep 8, 2023 · 17de9c0 · 17de9c0
1 parent f9d8953
commit 17de9c0
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diff --git a/boards/xtensa/m5stack_core2/grove_connectors.dtsi b/boards/xtensa/m5stack_core2/grove_connectors.dtsi
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2023 Joel Guittet
+ * Copyright (c) 2023 Martin Kiepfer
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	grove_header: grove_header {
+		compatible = "grove-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio1 1 0>,    /* D0/SCL/RX */
+				<1 0 &gpio1 0 0>;    /* D1/SDA/TX */
+	};
+};
+
+grove_i2c: &i2c1 {};
+grove_uart: &uart1 {};
diff --git a/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi b/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi
@@ -20,6 +20,14 @@
 		bias-pull-up;
 	};
 
+	uart1_rx_gpio33: uart1_rx_gpio33 {
+		pinmux = <UART1_RX_GPIO33>;
+	};
+
+	uart1_tx_gpio32: uart1_tx_gpio32 {
+		pinmux = <UART1_TX_GPIO32>;
+	};
+
 	spim3_default: spim3_default {
 		group1 {
 			pinmux = <SPIM3_MISO_GPIO38>,
@@ -53,4 +61,13 @@
 		};
 	};
 
+	i2c1_default: i2c1_default {
+		group1 {
+			pinmux = <I2C1_SDA_GPIO32>,
+				 <I2C1_SCL_GPIO33>;
+			drive-open-drain;
+			output-high;
+		};
+	};
+
 };
diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.dts b/boards/xtensa/m5stack_core2/m5stack_core2.dts
@@ -7,6 +7,7 @@
 
 #include <espressif/esp32/esp32_common.dtsi>
 #include "m5stack_core2-pinctrl.dtsi"
+#include "grove_connectors.dtsi"
 #include <zephyr/dt-bindings/display/ili9xxx.h>
 #include <zephyr/dt-bindings/regulator/axp192.h>
 
@@ -63,6 +64,13 @@
 	pinctrl-names = "default";
 };
 
+&uart1 {
+	status = "disabled";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_rx_gpio33 &uart1_tx_gpio32>;
+	pinctrl-names = "default";
+};
+
 &gpio0 {
 	status = "okay";
 };
@@ -157,6 +165,15 @@
 	};
 };
 
+&i2c1 {
+	status = "disabled";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	sda-gpios = <&gpio0 32 GPIO_OPEN_DRAIN>;
+	scl-gpios = <&gpio0 33 GPIO_OPEN_DRAIN>;
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-names = "default";
+};
+
 &spi3 {
 	#address-cells = <1>;
 	#size-cells = <0>;