board: Google Twinkie V2

This is a new board for the google Twinkie V2 tool.

Signed-off-by: Jason Yuan <[email protected]>

boards/arm/google_twinkie_v2/Kconfig.board

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+# Google Twinkie V2 board configuration
+
+# Copyright 2023 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GOOGLE_TWINKIE_V2
+	bool "Google Twinkie V2 Board"
+	depends on SOC_STM32G474XX

boards/arm/google_twinkie_v2/Kconfig.defconfig

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+# Google Twinkie V2 board configuration
+
+# Copyright 2023 The ChromiumOS Authors
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_GOOGLE_TWINKIE_V2
+
+config BOARD
+	default "google_twinkie_v2"
+
+endif # BOARD_GOOGLE_TWINKIE_V2

boards/arm/google_twinkie_v2/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
+
+include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)

boards/arm/google_twinkie_v2/google_twinkie_v2.dts

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+/*
+ * Copyright 2023 The ChromiumOS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/g0/stm32g0b1Xe.dtsi>
+#include <st/g0/stm32g0b1r(b-c-e)ixn-pinctrl.dtsi>
+
+/ {
+	model = "Google Twinkie V2";
+	compatible = "google,twinkie-v2";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,shell_uart = &cdc_acm_uart0;
+		zephyr,console = &cdc_acm_uart1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		red_led_0: led0 {
+			gpios = <&gpioc 8 GPIO_ACTIVE_LOW>;
+		};
+		green_led_1: led1 {
+			gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;
+		};
+		blue_led_2: led2 {
+			gpios = <&gpiob 7 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	cc_config {
+		compatible = "gpio-leds";
+		cc1_en: cc1en {
+			gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		cc2_en: cc2en {
+			gpios = <&gpiob 13 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		dfu_detect: dfudetect {
+			gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+		};
+	};
+
+	cc1_buf: cc1buf {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 1>;
+		output-ohms = <0>;
+	};
+
+	cc2_buf: cc2buf {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 3>;
+		output-ohms = <0>;
+	};
+
+	vbus_v: vbusv {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 15>;
+		output-ohms = <68000>;
+		full-ohms = <(2000000 + 68000)>;
+	};
+
+	vbus_c: vbusc {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 17>;
+		output-ohms = <49900>;
+		full-ohms = <(330000 + 49900)>;
+	};
+
+	vcon_c: vconc {
+		compatible = "voltage-divider";
+		io-channels = <&adc1 18>;
+		output-ohms = <0>;
+	};
+
+
+	aliases {
+		led0 = &red_led_0;
+		led1 = &green_led_1;
+		led2 = &blue_led_2;
+		bootloader-led0 = &blue_led_2;
+		encc1 = &cc1_en;
+		encc2 = &cc2_en;
+		vcc1 = &cc1_buf;
+		vcc2 = &cc2_buf;
+		vbus = &vbus_v;
+		cbus = &vbus_c;
+		ccon = &vcon_c;
+	};
+};
+
+
+&adc1 {
+	pinctrl-0 = <&adc1_in1_pa1	/* CC1_BUF	 */
+		     &adc1_in3_pa3	/* CC2_BUF	 */
+		     &adc1_in15_pb11	/* VBUS_READ_BUF */
+		     &adc1_in17_pc4	/* CSA_VBUS	 */
+		     &adc1_in18_pc5	/* CSA_CC2	 */
+		    >;
+
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&pll {
+	div-m = <1>;
+	mul-n = <8>;
+	div-p = <2>;
+	div-q = <2>;
+	div-r = <2>;
+	clocks = <&clk_hsi>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(64)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&ucpd1 {
+	status = "okay";
+
+	/*
+	 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
+	 * a prescaler who's output feeds the 'half-bit' divider which is used
+	 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
+	 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
+	 * range is 9 <--> 18 MHz.
+	 *
+	 *          +-------+ @ 16 MHz +-------+   @ ~600 kHz   +-----------+
+	 * HSI ---->| /psc  |--------->| /hbit |--------------->| trans_cnt |
+	 *          +-------+          +-------+   |            +-----------+
+	 *                                         |            +-----------+
+	 *                                         +----------->| ifrgap_cnt|
+	 *                                                      +-----------+
+	 * Requirements:
+	 *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
+	 *   2. tTransitionWindow - 12 to 20 uSec
+	 *   3. tInterframGap - uSec
+	 *
+	 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
+	 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
+	 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
+	 */
+	psc-ucpdclk = <1>;
+	hbitclkdiv = <27>;
+	pinctrl-0 = <&ucpd1_cc1_pa8 &ucpd1_cc2_pb15>;
+	pinctrl-names = "default";
+};
+
+zephyr_udc0: &usb {
+	/* Twinkie V2 Command Shell */
+	cdc_acm_uart0: cdc_acm_uart0 {
+		compatible = "zephyr,cdc-acm-uart";
+	};
+
+	/* Twinkie V2 Packet Logging */
+	cdc_acm_uart1: cdc_acm_uart1 {
+		compatible = "zephyr,cdc-acm-uart";
+	};
+
+	pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
+	pinctrl-names = "default";
+	status = "okay";
+};

boards/arm/google_twinkie_v2/google_twinkie_v2.yaml

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+identifier: google_twinkie_v2
+name: Goolge Twinkie PD Snooper
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 36
+flash: 128
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig

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+# Copyright 2023 The ChromiumOS Authors
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_STM32G0X=y
+CONFIG_SOC_STM32G0B1XX=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Enable Clocks
+CONFIG_CLOCK_CONTROL=y
+
+# enable pin controller
+CONFIG_PINCTRL=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y