drivers: adc: Add support ADC for Renesas RA4

- Support ADC for RA4E2, RA4M2, RA4M3, RA4W1 - Initial overlays for RA4 in test app adc_accuracy_test, adc_api Signed-off-by: Khoa Nguyen <[email protected]>
zephyrproject-rtos · Nov 1, 2024 · aac4e23 · aac4e23
1 parent d6e174b
commit aac4e23
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diff --git a/boards/renesas/ek_ra4e2/doc/index.rst b/boards/renesas/ek_ra4e2/doc/index.rst
@@ -98,6 +98,8 @@ The below features are currently supported on Zephyr OS for EK-RA4E2 board:
 +-----------+------------+----------------------+
 | CLOCK     | on-chip    | clock control        |
 +-----------+------------+----------------------+
+| ADC       | on-chip    | adc                  |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 

diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi
@@ -11,4 +11,12 @@
 			<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
 		};
 	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0, 0)>;
+			renesas,analog-enable;
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts
@@ -7,6 +7,7 @@
 
 #include <renesas/ra/ra4/r7fa4e2b93cfm.dtsi>
 #include <dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 #include "ek_ra4e2-pinctrl.dtsi"
 
 / {
@@ -76,3 +77,9 @@
 &ioport2 {
 	status = "okay";
 };
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/renesas/ek_ra4m2/doc/index.rst b/boards/renesas/ek_ra4m2/doc/index.rst
@@ -98,6 +98,8 @@ The below features are currently supported on Zephyr OS for EK-RA4M2 board:
 +-----------+------------+----------------------+
 | CLOCK     | on-chip    | clock control        |
 +-----------+------------+----------------------+
+| ADC       | on-chip    | adc                  |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 

diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi
@@ -11,4 +11,12 @@
 			<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
 		};
 	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0, 0)>;
+			renesas,analog-enable;
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts
@@ -7,6 +7,7 @@
 
 #include <renesas/ra/ra4/r7fa4m2ad3cfp.dtsi>
 #include <dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 #include "ek_ra4m2-pinctrl.dtsi"
 
 / {
@@ -72,3 +73,9 @@
 &ioport4 {
 	status = "okay";
 };
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/renesas/ek_ra4m3/doc/index.rst b/boards/renesas/ek_ra4m3/doc/index.rst
@@ -100,6 +100,8 @@ The below features are currently supported on Zephyr OS for EK-RA4M3 board:
 +-----------+------------+----------------------+
 | CLOCK     | on-chip    | clock control        |
 +-----------+------------+----------------------+
+| ADC       | on-chip    | adc                  |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 

diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi
@@ -11,4 +11,12 @@
 			<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
 		};
 	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0, 0)>;
+			renesas,analog-enable;
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts
@@ -7,6 +7,7 @@
 
 #include <renesas/ra/ra4/r7fa4m3af3cfb.dtsi>
 #include <dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 #include "ek_ra4m3-pinctrl.dtsi"
 
 / {
@@ -72,3 +73,9 @@
 &ioport4 {
 	status = "okay";
 };
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/renesas/ek_ra4w1/doc/index.rst b/boards/renesas/ek_ra4w1/doc/index.rst
@@ -90,6 +90,8 @@ The below features are currently supported on Zephyr OS for EK-RA4W1 board:
 +-----------+------------+----------------------+
 | CLOCK     | on-chip    | clock control        |
 +-----------+------------+----------------------+
+| ADC       | on-chip    | adc                  |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 

diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi
@@ -11,4 +11,12 @@
 			<RA_PSEL(RA_PSEL_SCI_0, 1, 0)>;
 		};
 	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0, 4)>;
+			renesas,analog-enable;
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.dts b/boards/renesas/ek_ra4w1/ek_ra4w1.dts
@@ -7,6 +7,7 @@
 
 #include <renesas/ra/ra4/r7fa4w1ad2cng.dtsi>
 #include <dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 #include "ek_ra4w1-pinctrl.dtsi"
 
 / {
@@ -59,3 +60,9 @@
 &ioport4 {
 	status = "okay";
 };
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
@@ -7,6 +7,8 @@
 #include <zephyr/dt-bindings/clock/ra_clock.h>
 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
 
+/delete-node/ &adc1;
+
 / {
 	soc {
 		sram0: memory@20000000 {
@@ -34,6 +36,11 @@
 			};
 		};
 
+		adc0: adc@40170000 {
+			channel-count = <12>;
+			channel-available-mask = <0x139f7>;
+		};
+
 		id_code: id_code@100a120 {
 			compatible = "zephyr,memory-region";
 			reg = <0x0100a120 0x10>;

diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
@@ -7,6 +7,8 @@
 #include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
 #include <zephyr/dt-bindings/clock/ra_clock.h>
 
+/delete-node/ &adc1;
+
 / {
 	soc {
 		sram0: memory@20000000 {
@@ -89,6 +91,11 @@
 				status = "disabled";
 			};
 		};
+
+		adc0: adc@40170000 {
+			channel-count = <13>;
+			channel-available-mask = <0x139ff>;
+		};
 	};
 
 	clocks: clocks {

diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
@@ -99,6 +99,16 @@
 				status = "disabled";
 			};
 		};
+
+		adc0: adc@40170000 {
+			channel-count = <12>;
+			channel-available-mask = <0x33ff>;
+		};
+
+		adc1: adc@40170200 {
+			channel-count = <10>;
+			channel-available-mask = <0x7f0007>;
+		};
 	};
 
 	clocks: clocks {

diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
@@ -7,6 +7,8 @@
 #include <zephyr/dt-bindings/clock/ra_clock.h>
 #include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
 
+/delete-node/ &adc1;
+
 / {
 	soc {
 		sram0: memory@20000000 {
@@ -34,6 +36,12 @@
 				status = "disabled";
 			};
 		};
+
+		adc0: adc@4005c000 {
+			interrupts = <20 1>;
+			channel-count = <8>;
+			channel-available-mask = <0x1a0670>;
+		};
 	};
 
 	clocks: clocks {

diff --git a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi
@@ -137,6 +137,26 @@
 			};
 		};
 
+		adc0: adc@40170000 {
+			compatible = "renesas,ra-adc";
+			interrupts = <40 1>;
+			interrupt-names = "scanend";
+			reg = <0x40170000 0x100>;
+			#io-channel-cells = <1>;
+			vref-mv = <3300>;
+			status = "disabled";
+		};
+
+		adc1: adc@40170200 {
+			compatible = "renesas,ra-adc";
+			interrupts = <41 1>;
+			interrupt-names = "scanend";
+			reg = <0x40170200 0x100>;
+			#io-channel-cells = <1>;
+			vref-mv = <3300>;
+			status = "disabled";
+		};
+
 		option_setting_ofs: option_setting_ofs@100a100 {
 			compatible = "zephyr,memory-region";
 			reg = <0x0100a100 0x18>;

diff --git a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi
@@ -160,6 +160,24 @@
 			};
 		};
 
+		adc0: adc@4005c000 {
+			compatible = "renesas,ra-adc";
+			interrupt-names = "scanend";
+			reg = <0x4005c000 0x100>;
+			#io-channel-cells = <1>;
+			vref-mv = <3300>;
+			status = "disabled";
+		};
+
+		adc1: adc@4005c200 {
+			compatible = "renesas,ra-adc";
+			interrupt-names = "scanend";
+			reg = <0x4005c200 0x100>;
+			#io-channel-cells = <1>;
+			vref-mv = <3300>;
+			status = "disabled";
+		};
+
 		id_code: id_code@1010018 {
 			compatible = "zephyr,memory-region";
 			reg = <0x01010018 0x20>;

diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>;
+		reference_mv = <3300>;
+		expected_accuracy = <32>;
+	};
+};
+
+&adc0{
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <3300>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>;
+		reference_mv = <3300>;
+		expected_accuracy = <32>;
+	};
+};
+
+&adc0{
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <3300>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>;
+		reference_mv = <3300>;
+		expected_accuracy = <32>;
+	};
+};
+
+&adc0{
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <3300>;
+	};
+};