soc/xtensa/intel_adsp: Disable L2 cache at boot based on Kconfig

Instead of deciding based on SoC version, add information to Kconfig and get it from there on code. Signed-off-by: Ederson de Souza <[email protected]>
zephyrproject-rtos · Sep 8, 2022 · cf6bad7 · cf6bad7
1 parent fcdc9c7
commit cf6bad7
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Showing 3 changed files with 6 additions and 6 deletions.
diff --git a/soc/xtensa/intel_adsp/Kconfig b/soc/xtensa/intel_adsp/Kconfig
@@ -90,4 +90,7 @@ config ADSP_INIT_HPSRAM
 	help
 	  Need to init HP SRAM.
 
+config ADSP_DISABLE_L2CACHE_AT_BOOT
+	bool
+
 endif # SOC_FAMILY_INTEL_ADSP
diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15 b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15
@@ -49,4 +49,6 @@ endif # DAI_INTEL_SSP
 config ADSP_INIT_HPSRAM
 	default n
 
+config ADSP_DISABLE_L2CACHE_AT_BOOT
+	default y
 endif
diff --git a/soc/xtensa/intel_adsp/common/boot.c b/soc/xtensa/intel_adsp/common/boot.c
@@ -41,11 +41,6 @@
 #define HOST_PAGE_SIZE		4096
 #define MANIFEST_SEGMENT_COUNT	3
 
-/* FIXME: Use Kconfig or some other means */
-#if defined(CONFIG_SOC_INTEL_CAVS_V15)
-#define PLATFORM_DISABLE_L2CACHE_AT_BOOT
-#endif
-
 /* FIXME: Use Kconfig or some other means */
 #if !defined(CONFIG_SOC_SERIES_INTEL_ACE1X)
 #define RESET_MEMORY_HOLE
@@ -161,7 +156,7 @@ __imr void boot_core0(void)
 {
 	cpu_early_init();
 
-#ifdef PLATFORM_DISABLE_L2CACHE_AT_BOOT
+#ifdef CONFIG_ADSP_DISABLE_L2CACHE_AT_BOOT
 	ADSP_L2PCFG_REG = 0;
 #endif