soc: add OpenHW Group CVA6 SoC #77732
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carlescufi
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| # Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH | |||
| # SPDX-License-Identifier: Apache-2.0 | |||
| config BOARD_CV32A6_ARTY_A7_100 | |||
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split this into commits, not going to review 77 files spanning multiple boards, multiple socs and even samples in a single commits
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I have removed the boards and samples from this PR and created new PRs:
- boards: openhwgroup: add CV64A6 on GenesysII board #81019
- boards: openhwgroup: add CVA6 on GenesysII board #81015
- boards: openhwgroup: add CVA6 on Arty A7 board #81018
- boards: openhwgroup: add CVA6 Testbench #81017
I have kept the 32-bit and the 64-bit variants of the same board in the same PR, as they are otherwise identical.
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Have this PR have a soc (in one commit), drivers (each in different commits) and one board (in another commit), then once that is merged you can add additional boards in a new PR each with their own commit
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The Ethernet subsystem is not specific to this hardware (e.g., it is also used on ARM boards), so I will leave it as separate PRs.
This PR now has one commit with the SoC and one with a board in 32 and 64 bit variants.
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@WorldofJARcraft please don't forget that new boards must come with associated documentation. See https://docs.zephyrproject.org/latest/hardware/porting/board_porting.html#contributing-your-board |
Thank you for the reminder, I will finalize my changes and add the documentation before un-drafting the PR. |
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Adds support for the CVA6 family of RISC-V CPUs. CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available. This commit adds support for the 32-bit and 64-bit configurations of CVA6, as well as three slightly different SoCs (a minimal 32-bit configuration, a 64-bit configuration without FPU, a 64-bit configuration with FPU). Signed-off-by: Eric Ackermann <[email protected]>
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Adds support for the CVA6 CPU on a GenesysII FPGA board (https://github.com/openhwgroup/cva6). The SoC currently contains the CVA6 CPU with the SV39 MMU, interrupt controllers (CLINT and PLIC), UART, a SPI for booting from SD, a boot ROM, and I2C controller for on-board audio, a GPIO and the lowRISC ethernet subsystem. Two slightly different versions of the board are added, with a 64-bit and a 64-bit configuration of CVA6, respectively. Signed-off-by: Eric Ackermann <[email protected]>
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| // SPDX-License-Identifier: Apache-2.0 | |||
| status = "okay"; | ||
| compatible = "riscv"; | ||
| riscv,isa = "rv32ima"; | ||
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| }; | ||
| }; | ||
| }; | ||
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| reg = <0x80000000 0x40000000>; | ||
| status="okay"; | ||
| }; | ||
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| ranges; | ||
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| memory0:memory@80000000 { | ||
| device_type = "memory"; |
| default "cv32a6" if SOC_SERIES_CV32A6 | ||
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| config SOC | ||
| default "cv32a6" if SOC_CV32A6 |
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do you really need a soc series and a soc if they are the same value? If not, remove the soc series from Kconfig and soc.yml and just have the soc
| # SPDX-License-Identifier: Apache-2.0 | ||
| # RISCV64 OpenHW Group cva6 configuration options | ||
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| config SOC_CV64A6_IMAFDC |
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have a config SOC_CV64A6 symbol which selects common this, then you can select the unique ones in the separate Kconfigs. And select the common Kconfig from Kconfig.soc
| default "cv64a6" if SOC_CV64A6_IMAFDC | ||
| default "cv64a6" if SOC_CV64A6_IMAC |
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| default "cv64a6" if SOC_CV64A6_IMAFDC | |
| default "cv64a6" if SOC_CV64A6_IMAC | |
| default "cv64a6" if SOC_CV64A6 |
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| #include <stdint.h> | ||
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| void z_cva6_finish_test(const int32_t status); |
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| #include "cva6.dtsi" | ||
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| // minimal configuration of CVA6 32-bit CPUs: no instruction set extensions, |
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Capitalise first letter of comments i.e. English
Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs. Different configurations and instruction set extensions can be configured, and different SoCs targeting various FPGA boards are available.
This commit adds support for the 64-bit configuration of CVA6, as well as two slightly different SoCs (the main difference being the Ethernet subsystem).
The configuration can also optionally target the hardware simulation environment (test harness) of the CVA6 project and can indicate test/failure to the environment.