Add support Flash QSPI on S32Z270 #78073
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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Hello @nordicjm, after some consideration, I added the |
| Memory alignment in bytes, used to calculate padding when performing | ||
| unaligned accesses. | ||
| If not provided, 1 byte alignment will be selected. | ||
| The number of bytes used in write operations, it also used to calculate padding when |
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Still mentioning padding.
| { | ||
| Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev); | ||
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| return ((offset >= 0) && (offset < memory_cfg->memSize) && |
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if size and offset get large enough you can get into situation where they overflow and you and up having true in line 22, even though parameters are out of range.
More proper would be to do:
return (offset >= 0 && offset < memory_cfg->memSize && ((memory_cfg->mem_size - offset) >= size)
drivers/flash/flash_nxp_s32_qspi.c
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| if (!area_is_subregion(dev, offset, size)) { | ||
| return -ENODEV; |
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I am quite sure other drivers return -EINVAL here.
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There is no check of offset nor size for alignment to write-block-size set in DTS, I know that device permits 1, but if you set it to something else and let to be ignored, this will allow different subsystems write/read with different alignment and produce data that they may not be able mutually read from the same device.
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I addressed comment. could you please revisit? @de-nordic
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Hello @de-nordic, could you revisit this PR? thanks. |
Following the commit f98fde0, DT_REG_ADDR now expands with a 'U' suffix as an unsigned value. However, for compatibility with IS_EQ, a raw value without any suffix is required. Therefore, this update is necessary. Signed-off-by: Cong Nguyen Huu <[email protected]>
Add support QSPI secure flash protection (SFP) Signed-off-by: Cong Nguyen Huu <[email protected]>
Create common source code to use for supporting HyperFlash. Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to 'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig. Add the 'max-program-buffer-size' property to use for setting memory pageSize, instead of using 'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting. Add the 'write-block-size' propertyto use for setting the number of bytes used in write operations, it also uses to instead of the 'memory-alignment' property. Signed-off-by: Cong Nguyen Huu <[email protected]>
Add support HyperFlash memory devices on a NXP S32 QSPI bus. This driver uses a fixed LUT configuration that defined in HAL RTD HyperFlash driver. Driver allows to read, write and erase HyperFlash devices. Signed-off-by: Cong Nguyen Huu <[email protected]>
The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller port A1. This board configuration selects it as the default flash controller. Signed-off-by: Cong Nguyen Huu <[email protected]>
Enable flash samples for s32z board Signed-off-by: Cong Nguyen Huu <[email protected]>
Enable flash tests for s32z board Signed-off-by: Cong Nguyen Huu <[email protected]>
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I rebased to fix conflict file west manifest |
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Hello @dleach02, @manuargue and @de-nordic. Is there any chance that this PR can be merged before the freeze? Thanks. |
| if (status != STATUS_QSPI_IP_SUCCESS) { | ||
| LOG_ERR("Failed to read memory status (%d)", status); | ||
| ret = -EIO; | ||
| } else if (timeout <= 0) { |
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timeout will never be negative, it is uint32_t
| do { | ||
| status = Qspi_Ip_GetMemoryStatus(data->instance); | ||
| timeout--; | ||
| } while ((status == STATUS_QSPI_IP_BUSY) && (timeout > 0)); |
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You really want to busy loop here? Is there any idling in Qspi_Ip_GetMemoryStatus ?
| size_t max_write = (size_t)MIN(QSPI_IP_MAX_WRITE_SIZE, memory_cfg->pageSize); | ||
| size_t len; | ||
| int ret = 0; | ||
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is size is 0 there is a lot happening, without write, that could be just bypassed.
| Qspi_Ip_StatusType status; | ||
| size_t erase_size; | ||
| int ret = 0; | ||
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Same here, why not just exit when size is 0?
Introduce support HyperFlash memory devices on a NXP S32 QSPI bus. This driver uses a fixed LUT configuration that defined in HAL RTD HyperFlash driver and allows to read, write, and erase HyperFlash devices.
Add support QSPI secure flash protection (SFP) for memory control NXP S32 QSPI.
Enable support Flash QSPI on S32Z2XX, the on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller port A1. This board configuration selects it as the default flash controller.
The test result: