Add support Flash QSPI on S32Z270 #78073
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Needs to be sequenced behind #81012
@congnguyenhuu I merged the HAL side. After the gating PR merges, then we can update the HAL SHA and I'll clear my CR
Following the commit f98fde0, DT_REG_ADDR now expands with a 'U' suffix as an unsigned value. However, for compatibility with IS_EQ, a raw value without any suffix is required. Therefore, this update is necessary. Signed-off-by: Cong Nguyen Huu <[email protected]>
Add support QSPI secure flash protection (SFP) Signed-off-by: Cong Nguyen Huu <[email protected]>
Create common source code to use for supporting HyperFlash. Rename 'FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME' to 'FLASH_NXP_S32_QSPI_SFDP_RUNTIME' as a common kconfig. Add the 'max-program-buffer-size' property to use for setting memory pageSize, instead of using 'CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE' for setting. Add the 'write-block-size' propertyto use for setting the number of bytes used in write operations, it also uses to instead of the 'memory-alignment' property. Signed-off-by: Cong Nguyen Huu <[email protected]>
Add support HyperFlash memory devices on a NXP S32 QSPI bus. This driver uses a fixed LUT configuration that defined in HAL RTD HyperFlash driver. Driver allows to read, write and erase HyperFlash devices. Signed-off-by: Cong Nguyen Huu <[email protected]>
The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller port A1. This board configuration selects it as the default flash controller. Signed-off-by: Cong Nguyen Huu <[email protected]>
Enable flash samples for s32z board Signed-off-by: Cong Nguyen Huu <[email protected]>
Enable flash tests for s32z board Signed-off-by: Cong Nguyen Huu <[email protected]>
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I updated the HAL SHA |
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@de-nordic , could you please re-approve. Lost your approval when updating the HAL SHA |
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Introduce support HyperFlash memory devices on a NXP S32 QSPI bus. This driver uses a fixed LUT configuration that defined in HAL RTD HyperFlash driver and allows to read, write, and erase HyperFlash devices.
Add support QSPI secure flash protection (SFP) for memory control NXP S32 QSPI.
Enable support Flash QSPI on S32Z2XX, the on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller port A1. This board configuration selects it as the default flash controller.
The test result: