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Add rt700 lpadc support #84361

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Add rt700 lpadc support #84361

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4222470
dts: arm: nxp: add adc instances for RT700
lucien-nxp Dec 22, 2024
9112903
boards: nxp: mimxrt700_evk: add lpadc0 support
lucien-nxp Dec 22, 2024
aa4b2bf
tests: driver: adc: support adc_api case for mimxrt700_evk
lucien-nxp Dec 22, 2024
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6 changes: 6 additions & 0 deletions boards/nxp/mimxrt700_evk/board.c
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Original file line number Diff line number Diff line change
Expand Up @@ -318,6 +318,12 @@ void board_early_init_hook(void)
CLOCK_EnableClock(kCLOCK_Gpio10);
RESET_ClearPeripheralReset(kGPIO10_RST_SHIFT_RSTn);
#endif

#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpadc0), okay)
CLOCK_AttachClk(kFRO1_DIV1_to_SENSE_MAIN);
CLOCK_AttachClk(kSENSE_BASE_to_ADC);
CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1U);
#endif
}

static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)
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2 changes: 2 additions & 0 deletions boards/nxp/mimxrt700_evk/doc/index.rst
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Expand Up @@ -71,6 +71,8 @@ the hardware features below.
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+

The default configuration can be found in the defconfig file:

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10 changes: 10 additions & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi
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Expand Up @@ -33,4 +33,14 @@
drive-strength = "normal";
};
};

pinmux_lpadc0: pinmux_lpadc0 {
group0 {
pinmux = <ADC0_CH0_PIO10_0>,
<ADC0_CH1_PIO10_2>;
slew-rate = "normal";
drive-strength = "normal";
nxp,analog-mode;
};
};
};
6 changes: 6 additions & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts
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Expand Up @@ -83,6 +83,12 @@
status = "okay";
};

&lpadc0 {
status = "okay";
pinctrl-0 = <&pinmux_lpadc0>;
pinctrl-names = "default";
};

&blue_led {
status = "okay";
};
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1 change: 1 addition & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml
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Expand Up @@ -16,4 +16,5 @@ toolchain:
supported:
- gpio
- uart
- adc
vendor: nxp
6 changes: 6 additions & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts
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Expand Up @@ -46,6 +46,12 @@
};
};

&lpadc0 {
status = "okay";
pinctrl-0 = <&pinmux_lpadc0>;
pinctrl-names = "default";
};

&systick {
status = "okay";
};
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1 change: 1 addition & 0 deletions boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -16,4 +16,5 @@ toolchain:
supported:
- gpio
- uart
- adc
vendor: nxp
17 changes: 17 additions & 0 deletions dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi
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Expand Up @@ -6,6 +6,7 @@

#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
Expand Down Expand Up @@ -107,6 +108,22 @@
* and secure modes (0x50000000).
*/

lpadc0: adc@20c000 {
compatible = "nxp,lpc-lpadc";
reg = <0x20c000 0x304>;
interrupts = <15 0>;
status = "disabled";
clk-divider = <1>;
clk-source = <0>;
voltage-ref= <1>;
calibration-average = <128>;
power-level = <0>;
offset-value-a = <10>;
offset-value-b = <10>;
#io-channel-cells = <1>;
clocks = <&clkctl3 MCUX_LPADC1_CLK>;
};

rstctl0: reset@0 {
compatible = "nxp,rstctl";
reg = <0x0 0x1000>;
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17 changes: 17 additions & 0 deletions dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi
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Expand Up @@ -6,6 +6,7 @@

#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
Expand Down Expand Up @@ -90,6 +91,22 @@
* and secure modes (0x50000000).
*/

lpadc0: adc@20c000 {
compatible = "nxp,lpc-lpadc";
reg = <0x20c000 0x304>;
interrupts = <15 0>;
status = "disabled";
clk-divider = <1>;
clk-source = <0>;
voltage-ref= <1>;
calibration-average = <128>;
power-level = <0>;
offset-value-a = <10>;
offset-value-b = <10>;
#io-channel-cells = <1>;
clocks = <&clkctl3 MCUX_LPADC1_CLK>;
};

rstctl1: reset@40000 {
compatible = "nxp,rstctl";
reg = <0x40000 0x1000>;
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36 changes: 36 additions & 0 deletions tests/drivers/adc/adc_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
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@@ -0,0 +1,36 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright 2025 NXP
*/

#include <zephyr/dt-bindings/adc/mcux-lpadc.h>

/ {
zephyr,user {
io-channels = <&lpadc0 0>, <&lpadc0 1>;
};
};

&lpadc0 {
#address-cells = <1>;
#size-cells = <0>;

channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_EXTERNAL0";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,input-positive = <MCUX_LPADC_CH0A>;
};

channel@1 {
reg = <1>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_EXTERNAL0";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,input-positive = <MCUX_LPADC_CH1A>;
};
};
36 changes: 36 additions & 0 deletions tests/drivers/adc/adc_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay
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@@ -0,0 +1,36 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright 2025 NXP
*/

#include <zephyr/dt-bindings/adc/mcux-lpadc.h>

/ {
zephyr,user {
io-channels = <&lpadc0 0>, <&lpadc0 1>;
};
};

&lpadc0 {
#address-cells = <1>;
#size-cells = <0>;

channel@0 {
reg = <0>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_EXTERNAL0";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,input-positive = <MCUX_LPADC_CH0A>;
};

channel@1 {
reg = <1>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_EXTERNAL0";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,input-positive = <MCUX_LPADC_CH1A>;
};
};
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