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Switch RMT clock source to 1MHz REF #22

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Switch RMT clock source to 1MHz REF #22

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a910a7e
Switch RMT clock source to 1MHz REF
RadekHvizdos Mar 31, 2021
814286d
Add RMT Clock selection logic
RadekHvizdos Apr 1, 2021
60a681a
Debug print RMT clock information
RadekHvizdos Apr 1, 2021
083f4a5
Whitespace fix
RadekHvizdos Apr 1, 2021
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16 changes: 16 additions & 0 deletions include/owb_rmt.h
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Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,22 @@
#include "freertos/queue.h"
#include "freertos/ringbuf.h"
#include "driver/rmt.h"
#include "soc/soc_caps.h"

#ifdef SOC_RMT_SUPPORT_REF_TICK
#define RMT_BASECLK_SRC RMT_BASECLK_REF
#define RMT_CLK_DIV 1

#elif SOC_RMT_SUPPORT_XTAL
#define RMT_BASECLK_SRC RMT_BASECLK_XTAL
#define RMT_CLK_DIV 40

#else
#define RMT_BASECLK_SRC RMT_BASECLK_APB
#define RMT_CLK_DIV 80

#endif


#ifdef __cplusplus
extern "C" {
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9 changes: 5 additions & 4 deletions owb_rmt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -370,35 +370,36 @@ static owb_status _init(owb_rmt_driver_info *info, gpio_num_t gpio_num,
#ifdef OW_DEBUG
ESP_LOGI(TAG, "RMT TX channel: %d", info->tx_channel);
ESP_LOGI(TAG, "RMT RX channel: %d", info->rx_channel);
ESP_LOGI(TAG, "RMT CLK_DIV: %d, BASECLK_SRC: %d", RMT_CLK_DIV, RMT_BASECLK_SRC);
#endif

rmt_config_t rmt_tx = {0};
rmt_tx.channel = info->tx_channel;
rmt_tx.gpio_num = gpio_num;
rmt_tx.mem_block_num = 1;
rmt_tx.clk_div = 80;
rmt_tx.clk_div = RMT_CLK_DIV;
rmt_tx.tx_config.loop_en = false;
rmt_tx.tx_config.carrier_en = false;
rmt_tx.tx_config.idle_level = 1;
rmt_tx.tx_config.idle_output_en = true;
rmt_tx.rmt_mode = RMT_MODE_TX;
if (rmt_config(&rmt_tx) == ESP_OK)
{
rmt_set_source_clk(info->tx_channel, RMT_BASECLK_APB); // only APB is supported by IDF 4.2
rmt_set_source_clk(info->tx_channel, RMT_BASECLK_SRC);
if (rmt_driver_install(rmt_tx.channel, 0, ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_SHARED) == ESP_OK)
{
rmt_config_t rmt_rx = {0};
rmt_rx.channel = info->rx_channel;
rmt_rx.gpio_num = gpio_num;
rmt_rx.clk_div = 80;
rmt_rx.clk_div = RMT_CLK_DIV;
rmt_rx.mem_block_num = 1;
rmt_rx.rmt_mode = RMT_MODE_RX;
rmt_rx.rx_config.filter_en = true;
rmt_rx.rx_config.filter_ticks_thresh = 30;
rmt_rx.rx_config.idle_threshold = OW_DURATION_RX_IDLE;
if (rmt_config(&rmt_rx) == ESP_OK)
{
rmt_set_source_clk(info->rx_channel, RMT_BASECLK_APB); // only APB is supported by IDF 4.2
rmt_set_source_clk(info->rx_channel, RMT_BASECLK_SRC);
if (rmt_driver_install(rmt_rx.channel, 512, ESP_INTR_FLAG_LOWMED | ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_SHARED) == ESP_OK)
{
rmt_get_ringbuf_handle(info->rx_channel, &info->rb);
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