Merge branch 'feat/icache' into wr_type

.vscode/settings.json

@@ -17,7 +17,8 @@
         "**/*"
     ],
     "todo-tree.filtering.useBuiltInExcludes": "file and search excludes",
-    "systemverilogFormatter.veribleBuild": "Ubuntu-20.04-focal-x86_64",
+    "systemverilogFormatter.veribleBuild": "none",
     "systemverilogFormatter.commandLineArguments": "--indentation_spaces 4",
-    "editor.formatOnSave": true
+    "editor.formatOnSave": true,
+    "verilog.ctags.path": "ctags"
 }

src/vsrc/core_config.sv

@@ -4,15 +4,19 @@
 
 package core_config;
 
+    // Global parameters
     parameter ADDR_WIDTH = 32;
     parameter DATA_WIDTH = 32;
 
-
     // Frontend Parameters
     parameter FETCH_WIDTH = 4;
     parameter ICACHELINE_WIDTH = 128;
     parameter FRONTEND_FTQ_SIZE = 8;
 
+    // ICache parameters
+    parameter ICACHE_NWAY = 2;
+    parameter ICACHE_NSET = 256;
+
     // Commit Parameters
     parameter COMMIT_WIDTH = 2;
 

src/vsrc/cpu_top.sv

@@ -279,6 +279,7 @@ module cpu_top
     logic [1:0][`InstAddrBus] frontend_icache_addr;
 
     // ICache -> Frontend
+    logic [1:0]icache_frontend_rreq_ack;
     logic [1:0]icache_frontend_valid;
     logic [1:0][ICACHELINE_WIDTH-1:0] icache_frontend_data;
 
@@ -291,28 +292,44 @@ module cpu_top
     logic [13:0] dispatch_csr_read_addr;
     logic [`RegBus] dispatch_csr_data;
 
+    logic icacop_op_en[2];
+    logic icacop_ack;
+    logic [1:0] cacop_op_mode[2];
+
     icache u_icache(
-       .clk          (clk          ),
-       .rst          (rst          ),
+        .clk          (clk          ),
+        .rst          (rst          ),
 
-       // Port A
-       .rreq_1_i     (frontend_icache_rreq[0]),
-       .raddr_1_i    (frontend_icache_addr[0]),
-       .rvalid_1_o   (icache_frontend_valid[0]),
-       .rdata_1_o    (icache_frontend_data[0]),
-       // Port B
-       .rreq_2_i     (frontend_icache_rreq[1]),
-       .raddr_2_i    (frontend_icache_addr[1]),
-       .rvalid_2_o   (icache_frontend_valid[1]),
-       .rdata_2_o    (icache_frontend_data[1]),
-
-       // <-> AXI Controller
-       .axi_addr_o   (icache_axi_addr),
-       .axi_rreq_o   (icache_axi_rreq),
-       .axi_rdy_i    (axi_icache_rdy),
-       .axi_rvalid_i (axi_icache_rvalid),
-       .axi_rlast_i  (),
-       .axi_data_i   (axi_icache_data),
+        // Port A
+        .rreq_1_i     (frontend_icache_rreq[0]),
+        .raddr_1_i    (frontend_icache_addr[0]),
+        .rreq_1_ack_o (icache_frontend_rreq_ack[0]),
+        .rvalid_1_o   (icache_frontend_valid[0]),
+        .rdata_1_o    (icache_frontend_data[0]),
+        // Port B
+        .rreq_2_i     (frontend_icache_rreq[1]),
+        .raddr_2_i    (frontend_icache_addr[1]),
+        .rreq_2_ack_o (icache_frontend_rreq_ack[1]),
+        .rvalid_2_o   (icache_frontend_valid[1]),
+        .rdata_2_o    (icache_frontend_data[1]),
+
+        // <-> AXI Controller
+        .axi_addr_o   (icache_axi_addr),
+        .axi_rreq_o   (icache_axi_rreq),
+        .axi_rdy_i    (axi_icache_rdy),
+        .axi_rvalid_i (axi_icache_rvalid),
+        .axi_rlast_i  (),
+        .axi_data_i   (axi_icache_data),
+
+        .frontend_uncache_i(),
+        .invalid_i(),
+
+        //-> CACOP
+        .cacop_i(icacop_op_en[0]),
+        .cacop_mode_i(cacop_op_mode[0]),
+        .cacop_addr_i({tlb_data_o.tag,tlb_data_o.index,tlb_data_o.offset}),
+        .cacop_ack_o(icacop_ack),
+
 
        // TLB related
        .tlb_i(tlb_inst), // <- TLB
@@ -338,6 +355,7 @@ module cpu_top
         // <-> ICache
         .icache_read_addr_o(frontend_icache_addr),  // -> ICache
         .icache_read_req_o(frontend_icache_rreq),
+        .icache_rreq_ack_i(icache_frontend_rreq_ack),
         .icache_read_valid_i(icache_frontend_valid),  // <- ICache
         .icache_read_data_i(icache_frontend_data),  // <- ICache
 
@@ -549,10 +567,11 @@ module cpu_top
                 .excp_flush(excp_flush),
                 .ertn_flush(ertn_flush),
 
-                // -> Cache
-                .icacop_op_en(icacop_op_en),
+                // <-> Cache
+                .icacop_op_en(icacop_op_en[i]),
+                .icacop_op_ack_i(icacop_ack),
                 .dcacop_op_en(dcacop_op_en),
-                .cacop_op_mode(dicacop_op_mode),
+                .cacop_op_mode(cacop_op_mode[i]),
 
                 // <-> Ctrl
                 .stall({mem_stallreq[0] | mem_stallreq[1] ,stall[3]}),
@@ -1065,10 +1084,10 @@ ila_1 ila_cpu_top (
 	.probe0(u_axi_master.inst_r_state), // input wire [3:0]  probe0  
 	.probe1(u_axi_master.data_r_state), // input wire [3:0]  probe1 
 	.probe2(u_axi_master.w_state), // input wire [3:0]  probe2 
-	.probe3({26'b0,u_axi_master.dcache_rd_type_i,u_axi_master.s_arsize}), // input wire [31:0]  probe3 
-	.probe4(u_axi_master.dcache_rd_req_i), // input wire [0:0]  probe4 
-	.probe5(u_axi_master.dcache_ret_valid_o), // input wire [0:0]  probe5 
-	.probe6(u_regfile.regs[4]), // input wire [31:0]  probe6 
+	.probe3({21'b0,u_icache.hit,u_icache.miss_1, u_icache.miss_2,u_icache.cacop_i,u_axi_master.dcache_rd_type_i,u_axi_master.s_arsize}), // input wire [31:0]  probe3 
+	.probe4(u_axi_master.icache_rd_req_i), // input wire [0:0]  probe4 
+	.probe5(u_axi_master.icache_ret_valid_o), // input wire [0:0]  probe5 
+	.probe6(u_icache.state), // input wire [31:0]  probe6 
 	.probe7(u_tlb.data_i.fetch), // input wire [0:0]  probe7 
 	.probe8(u_tlb.we), // input wire [0:0]  probe8 
 	.probe9(u_tlb.data_i.vaddr), // input wire [31:0]  probe9 

src/vsrc/frontend/frontend.sv

@@ -18,6 +18,7 @@ module frontend
     // ICache is fixed dual port
     output logic [1:0] icache_read_req_o,
     output logic [1:0][ADDR_WIDTH-1:0] icache_read_addr_o,
+    input logic [1:0] icache_rreq_ack_i,
     input logic [1:0] icache_read_valid_i,
     input logic [1:0][ICACHELINE_WIDTH-1:0] icache_read_data_i,
 
@@ -141,10 +142,11 @@ module frontend
         .tlb_o(tlb_o),
 
         // <-> Frontend <-> ICache
-        .icache_rreq_o  (icache_read_req_o),
-        .icache_raddr_o (icache_read_addr_o),
+        .icache_rreq_o(icache_read_req_o),
+        .icache_raddr_o(icache_read_addr_o),
+        .icache_rreq_ack_i(icache_rreq_ack_i),
         .icache_rvalid_i(icache_read_valid_i),
-        .icache_rdata_i (icache_read_data_i),
+        .icache_rdata_i(icache_read_data_i),
 
 
         // <-> Frontend <-> Instruction Buffer

src/vsrc/frontend/ftq.sv

@@ -87,7 +87,7 @@ module ftq
         next_FTQ = FTQ;
         // clear out if committed
         for (integer i = 0; i < COMMIT_WIDTH; i++) begin
-            if (backend_commit_i[i]) next_FTQ[comm_ptr+i] = 0;
+            if (i < backend_commit_num) next_FTQ[comm_ptr+i] = 0;
         end
         // Accept BPU input
         if (bpu_i.valid) next_FTQ[bpu_ptr] = bpu_i;

src/vsrc/frontend/ifu.sv

@@ -31,6 +31,7 @@ module ifu
     // <-> Frontend <-> ICache
     output logic [1:0] icache_rreq_o,
     output logic [1:0][ADDR_WIDTH-1:0] icache_raddr_o,
+    input logic [1:0] icache_rreq_ack_i,
     input logic [1:0] icache_rvalid_i,
     input logic [1:0][ICACHELINE_WIDTH-1:0] icache_rdata_i,
 
@@ -42,17 +43,18 @@ module ifu
     // P0 signal
     logic p0_send_rreq, p0_send_rreq_delay1;
     // P1 signal
+    logic p1_rreq_ack;
     logic p1_read_done;  // Read done is same cycle as ICache return valid
-    logic p1_stallreq;  // Currently in transaction and not done yet
+    logic p1_in_transaction;  // Currently in transaction and not done yet
     // Flush state
     logic is_flushing_r, is_flushing;
 
     /////////////////////////////////////////////////////////////////////////////////
     // P0, send read req to ICache & TLB
     /////////////////////////////////////////////////////////////////////////////////
     // Condition when to send rreq to ICache, see doc for detail
-    assign p0_send_rreq = ftq_i.valid & ~is_flushing & ~stallreq_i & ~p1_stallreq;
-    assign ftq_accept_o = p0_send_rreq;  // FTQ handshake, same cycle as ftq_i
+    assign p0_send_rreq = ftq_i.valid & ~is_flushing & ~stallreq_i & ~p1_in_transaction;
+    assign ftq_accept_o = p0_send_rreq;  // FTQ handshake, same cycle as ftq_i, FTQ can move to next block
     always_ff @(posedge clk) begin
         p0_send_rreq_delay1 <= p0_send_rreq;
     end
@@ -65,10 +67,6 @@ module ifu
     logic dmw0_en, dmw1_en;
     assign dmw0_en = ((csr_i.dmw0[`PLV0] && csr_i.plv == 2'd0) || (csr_i.dmw0[`PLV3] && csr_i.plv == 2'd3)) && (p0_pc[31:29] == csr_i.dmw0[`VSEG]); // Direct map window 0
     assign dmw1_en = ((csr_i.dmw1[`PLV0] && csr_i.plv == 2'd0) || (csr_i.dmw1[`PLV3] && csr_i.plv == 2'd3)) && (p0_pc[31:29] == csr_i.dmw1[`VSEG]); // Direct map window 1
-    assign tlb_o.dmw0_en = dmw0_en;
-    assign tlb_o.dmw1_en = dmw1_en;
-    assign tlb_o.trans_en = csr_i.pg && !csr_i.da && !dmw0_en && !dmw1_en; // Not in direct map windows, enable paging
-    assign tlb_o.vaddr = p0_pc;
 
     // Send read req to ICache & TLB
     always_comb begin
@@ -80,10 +78,22 @@ module ifu
             icache_raddr_o[1] = ftq_i.is_cross_cacheline ? {ftq_i.start_pc[ADDR_WIDTH-1:4], 4'b0} + 16 : 0; // TODO: remove magic number
             // Send req to TLB
             tlb_o.fetch = 1;
+            tlb_o.dmw0_en = dmw0_en;
+            tlb_o.dmw1_en = dmw1_en;
+            tlb_o.trans_en = csr_i.pg && !csr_i.da && !dmw0_en && !dmw1_en; // Not in direct map windows, enable paging
+            tlb_o.vaddr = p0_pc;
+        end else if (p1_in_transaction) begin
+            // Or P1 is in transaction
+            icache_rreq_o[0] = 1;
+            icache_rreq_o[1] = p1_read_transaction.is_cross_cacheline ? 1 : 0;
+            icache_raddr_o[0] = {p1_read_transaction.start_pc[ADDR_WIDTH-1:4], 4'b0};
+            icache_raddr_o[1] = p1_read_transaction.is_cross_cacheline ? {p1_read_transaction.start_pc[ADDR_WIDTH-1:4], 4'b0} + 16 : 0; // TODO: remove magic number
+            // Hold output to TLB
+            tlb_o = p1_read_transaction.tlb_rreq;
         end else begin
             icache_rreq_o = 0;
             icache_raddr_o = 0;
-            tlb_o.fetch = 0;
+            tlb_o = 0;
         end
     end
 
@@ -115,6 +125,7 @@ module ifu
         logic [`InstAddrBus] start_pc;
         logic is_cross_cacheline;
         logic [$clog2(`FETCH_WIDTH+1)-1:0] length;
+        logic [1:0] icache_rreq_ack_r;
         logic [1:0] icache_rvalid_r;
         logic [1:0][ICACHELINE_WIDTH-1:0] icache_rdata_r;
         logic [$clog2(FRONTEND_FTQ_SIZE)-1:0] ftq_id;
@@ -126,10 +137,13 @@ module ifu
     logic [ADDR_WIDTH-1:0] p1_pc;
     assign p1_pc = p1_read_transaction.start_pc;
 
+    assign p1_in_transaction = p1_read_transaction.valid & ~p1_read_done;
     assign p1_read_done = p1_read_transaction.is_cross_cacheline ?
-    (icache_rvalid_i[0] | p1_read_transaction.icache_rvalid_r[0]) & (icache_rvalid_i[1]| p1_read_transaction.icache_rvalid_r[1]) :
-    (icache_rvalid_i[0] | p1_read_transaction.icache_rvalid_r[0]);
-    assign p1_stallreq = p1_read_transaction.valid & ~p1_read_done;
+            (icache_rvalid_i[0] | p1_read_transaction.icache_rvalid_r[0]) & (icache_rvalid_i[1] | p1_read_transaction.icache_rvalid_r[1]) :
+            (icache_rvalid_i[0] | p1_read_transaction.icache_rvalid_r[0]);
+    assign p1_rreq_ack =  p1_read_transaction.is_cross_cacheline ?
+            (icache_rreq_ack_i[0] | p1_read_transaction.icache_rreq_ack_r[0]) & (icache_rreq_ack_i[1] | p1_read_transaction.icache_rreq_ack_r[1]) :
+            (icache_rreq_ack_i[0] | p1_read_transaction.icache_rreq_ack_r[0]);
     always_ff @(posedge clk) begin : p1_ff
         if (rst) begin
             p1_read_transaction <= 0;
@@ -139,6 +153,7 @@ module ifu
             p1_read_transaction.start_pc <= ftq_i.start_pc;
             p1_read_transaction.is_cross_cacheline <= ftq_i.is_cross_cacheline;
             p1_read_transaction.length <= ftq_i.length;
+            p1_read_transaction.icache_rreq_ack_r <= icache_rreq_ack_i;
             p1_read_transaction.icache_rvalid_r <= 0;
             p1_read_transaction.icache_rdata_r <= 0;
             p1_read_transaction.ftq_id <= ftq_id_i;
@@ -158,6 +173,9 @@ module ifu
                 p1_read_transaction.icache_rvalid_r[1] <= 1;
                 p1_read_transaction.icache_rdata_r[1]  <= icache_rdata_i[1];
             end
+            // Store ACK in P1 data structure
+            if (icache_rreq_ack_i[0]) p1_read_transaction.icache_rreq_ack_r <= 1;
+            if (icache_rreq_ack_i[1]) p1_read_transaction.icache_rreq_ack_r <= 1;
         end
     end
 
@@ -235,10 +253,5 @@ module ifu
         end
     end
 
-    // P2 Debug
-    logic debug_p2_tlb_trans_en;
-    logic [1:0] debug_p2_csr_plv;
-    assign debug_p2_tlb_trans_en = p1_read_transaction.tlb_rreq.trans_en;
-    assign debug_p2_csr_plv = p1_read_transaction.csr.plv;
 
 endmodule