UVM Model Output

Ordt will generate a UVM register abstraction layer model (uvm_reg) from a register definition input if the -uvmregs parameter is included in the ordt command. An output file containing design-specific block, and register class definitions will be created and will reference a systemverilog package of design-independent classes derived from uvm_reg base classes. The design-independent package can be optionally generated using the –uvmregspkg parameter.

####UVM model derived classes

Ordt creates a number of uvm_reg derived classes. The following design-independent uvm classes are generated and included in the ordt package:

• uvm_reg_block_rdl extends uvm_reg_block
• uvm_reg_rdl extends uvm_reg
• uvm_vreg_rdl extends uvm_vreg
• uvm_reg_field_rdl extends uvm_reg_field
• uvm_reg_field_rdl_counter extends uvm_reg_field_rdl
• uvm_reg_field_rdl_interrupt extends uvm_reg_field_rdl

In addition, design dependent classes are generated for registers and register sets:

• Design specific register classes extend uvm_reg_rdl
• Design specific block (register set/regfile/addrmap) classes extend uvm_reg_block_rdl

####Field methods in the UVM model

Ordt generates several field classes derived from uvm_reg_field that contain properties specified in the rdl input. This allows verification benches to access the model info for automated testing of these field types. If ordt generates the register rtl in addition to the uvm model, backdoor paths to registers and register I/O nets (eg counter increment signals) will be accessible in the model. Note that the hw paths in the uvm model assume the auto-generated RTL IO names are not overridden by the rdl (eg, through use of user-defined signals).

####Test control properties in the UVM model

Ordt adds a number of rdl/jspec properties to the uvm model for test control. At the uvm_reg_rdl level, these include:

• don't test property – intent to disable all tests of this register
• don't compare property – intent to disable checking of read data for this register
• jspec category – register classification

At the uvm_reg_field_rdl level, the following test control properties are accessible:

• don't compare property -> intent to disable checking of read data for this register
• jspec sub_category – field/interrupt classification

The volatile bit will be set at uvm_reg_field level under the following conditions:

• A field is determined to be hw writeable or modified by hw
• The don't compare property is set foe this field

####Memories in the UVM model

The uvmreg_is_mem property can be used to designate a replicated register as a uvm_mem to save memory space required to model large memories. If so designated, the register will be modeled as a uvm_mem with replicated virtual registers (uvm_vreg_rdl) rather than multiple uvm_regs. Note that use of virtual registers is a modeling construct, but has no direct correlation to physical implementation of on-chip memory.

To assist verification of virtual registers, an associative array of data values is added to uvm_vreg_rdl. This staged data array allows a very lightweight version of the mirroring supported in uvm_reg. Methods also handle bit shifting involved in setting or retrieving field values from a virtual register.

####UVM address coverpoints

UVM_CVR_ADDR_MAP coverpoints are added to the model if the include_address_coverage ordt control parameter is specified.

####Interrupts in the UVM model

Simple interrupt trees can be modeled in uvm output. Typically, this is specified in rdl by assigning the intr or halt output of an interrupt register to the next value of a field in an interrupt merge register. In the generated uvm model, interrupt fields representing the interrupt merge value will contain a reference to the driving child interrupt register. This allows interrupt (and halt) trees to be walked in the model for creation of interrupt handling routines, etc. SystemRDL interrupt mask/enable structure is also supported in the model for cases where the mask/enable is defined to be a field. Methods are provided to return the enabled/masked value of an interrupt field.

####Callbacks in the UVM model

In addition to the basic register functions modeled in the uvm ral, the uvm model generated by ordt includes callback support for modeling a subset of rdl-specified features:

• alias registers (multiple external addresses accessing the same physical register with different sw access policies)
• Interrupt fields affected by values of enable/mask fields via the maskintrbits property