UVM Model Output

Ordt will generate a UVM register abstraction layer model (uvm_reg) from a register definition input if the -uvmregs parameter is included in the ordt command. An output file containing design-specific block, and register class definitions will be created and will reference a systemverilog package of design-independent classes derived from uvm_reg base classes. The design-independent package can be optionally generated using the –uvmregspkg parameter.

####UVM model derived classes

Ordt creates a number of uvm_reg derived classes. The following design-independent uvm classes are generated and included in the ordt package:

• uvm_reg_block_rdl extends uvm_reg_block
• uvm_reg_rdl extends uvm_reg
• uvm_reg_field_rdl extends uvm_reg_field
• uvm_reg_field_rdl_counter extends uvm_reg_field_rdl
• uvm_reg_field_rdl_interrupt extends uvm_reg_field_rdl
• uvm_vreg_rdl extends uvm_vreg

Design dependent register and block (register_set/regfile) classes extend the uvm_reg_rdl and uvm_reg_block_rdl, respectively

TBD...

Uvm model field methods

Ordt generates several field classes derived from uvm_reg_field that contain properties specified in the rdl input. This allows verification benches to access the model info for automated testing of these field types. If ordt generates the register rtl in addition to the uvm model, backdoor paths to registers and register I/O nets (eg counter increment signals) will be accessible in the model. Note that the hw paths in the uvm model assume the auto-generated RTL IO names are not overridden by the rdl (eg, through use of user-defined signals).

Rdl field info is accessible via model (in addition to inherited uvm_reg_field methods) Field access methods: is_sw_readable(), is_sw_writeable(), is_hw_readable(), is_hw_writeable() Counter field methods: get_incr_value(), has_incr_sat(), get_decr_value(), etc Interrupt field methods: get_intr_level_type(), get_intr_sticky_type(), etc Field IO signal name methods: get_hw_we_signal(), get_overflow_signal(), get_intr_signal(), etc

In addition to the basic register functions modeled in the uvm ral, the uvm model generated by ordt includes callback support for modeling a subset of rdl-specified features: • Alias registers (multiple external addresses accessing the same physical register with different sw access policies) • Interrupt fields affected by values of enable/mask fields via the maskintrbits property interrupt hierarchy (see below)

SystemRDL properties affecting UVM register model output

Ordt allows the following boolean rdl register properties for control of testing: donttest– disable all tests of this register

The is_volatile bit in uvm_reg_field derived classes will be set if hardware modifies the field value or if the rdl dontcompare property is set for the field.

The uvmreg_is_mem property can be used to designate a replicated register as a uvm_mem to save memory space required to model large memories. If so designated, the register will be modeled as a uvm_mem with replicated virtual registers rather than multiple uvm_regs. -- is_mem Large replicated register arrays can be modeled as a uvm_reg_mem with virtual regs (uvm_vreg) to conserve memory This is only for reg model - has no correlation to physical memory

staged methods - poor mans mirror

test control: Field test control properties are accessible via model : rdl dontcompare property -> sets volatile bit in uvm field_rdl hw writeable fields -> sets volatile bit in uvm field_rdl Register test control properties are accessible via model: rdl donttest and dontcompare properties -> available in uvm_reg_rdl rdl category property - available in uvm_reg_rdl UVM address coverpoints:
UVM_CVR_ADDR_MAP coverpoints added to model if include_address_coverage control parameter is specified

Interrupts in the UVM model

Interrupt register hierarchy is in model: Interrupt fields representing interrupt merge value contain pointer to driving register Makes it possible to walk the interrupt tree on observed interrupt Callbacks in model keep parent merge fields in sync with child interrupt register status Rdl halt hierarchy is also supported (really an alternate intr) Interrupt enables/masks are in model: Interrupt fields that are enabled/masked by another field have a pointer to the field Methods are provided to return enabled/masked value, get_masked(), etc