uvm_reg_block_rdl methods

##uvm_reg_block_rdl class methods

uvm_reg_block_rdl extends the uvm_reg_block class to add rdl addrmap indication and functionality to build hierarchical RTL signal names from the UVM model.

###Methods:

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function void set_rdl_address_map()

Parameters:

• input bit val, (default value = 0)

Set indication that this block represents an rdl addrmap.

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function void set_rdl_address_map_hdl_path()

Parameters:

• input string path, (default value = "")

Set the root hdl path to the address map module that this block represents.

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function void set_rdl_tag()

Parameters:

• input string rdl_tag, (default value = "rdl_tag")

Set the rdl tag string for this block. The tag will be used to build RTL signal names using the model hierarchy.

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function string get_rdl_name()

Parameters:

• input string prefix
• input bit add_hdl_prefix, (default value = 0)
• input string override_tag, (default value = "")

Return a string corresponding to this model element using recursive call to ancestors (stopping at an address map). Used to generate RTL signal names.

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virtual function void add_callbacks()

Parameters:

Null function that is overridden by block/reg classes requiring callback setup.

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virtual function uvm_reg_block_rdl get_ancestor()

Parameters:

• input int depth

Return the uvm_reg_block_rdl element that is the specified number of ancestor levels from the current block/register.

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