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The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

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5-Stage-MIPS-Pipelined-with-Hazard-Mitigation

Pipelining, is a powerful way to improve the throughput of a digital system. We design a pipelined processor by subdividing the single-cycle processor into five pipeline stages. Thus, five instructions can execute simultaneously, one in each stage. Because each stage has only one-fifth of the entire logic, the clock frequency is almost five times faster. Hence, the latency of each instruction is ideally unchanged, but the throughput is ideally five times better.

pipeline abstract view

*Image taken from Digital Design and Computer Architecture by David Harris & Sarah Harris

Pipelining comes with hazards that designers must manage to achieve improved performance in pipelined architecture.

  1. Data Hazards: These occur when an instruction depends on the data results of a previous instruction that hasn’t yet completed its pipeline stage. For example, if an instruction requires a register value that a previous instruction is in the process of writing, it may need to wait or implement techniques such as forwarding or stalling to resolve this dependency.

  2. Control Hazards: These occur when the pipeline must make decisions based on conditional branches or jumps. When a branch instruction is encountered, the pipeline may not know which instruction to execute next until the branch condition is resolved. Techniques such as branch prediction, delayed branching, and speculative execution are often used to handle control hazards effectively.

Managing these hazards is essential to maintaining the efficiency of a pipelined processor and ensuring it delivers improved performance.

Below is the Proposed Architecture for MIPS Pipelined Architecture which takes care of both Data and Control Hazards.

image

*Image taken from Digital Design and Computer Architecture by David Harris & Sarah Harris

Below are the instructions Our Mips can Currenlty Execute

image

Below is the sample Test Code used for 5 stage Pipelined MIPS Processor.

image

Simulation Results Using ModelSim :-

new_simulation

Below is Power Required for Mips Processor Using Vivado :-

mips_power

Continuosly Bringing Improvements in Code-Base

Thank you

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The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

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