[#BZ104] Fix wrong instruction when adding two syms #41
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Change-Id: Icd1b11638dcca6ebe65db5cf44698e4038d34891
This reverts commit 0853501.
Change-Id: I4d1b41912d770abf4a6cc85e163f078be1cb91f1
... by reusing existing offset in CodeGenPrepare. Added NanoMipsCodeGenPrepare pass witch munges constant geps into a form that later can be optimized by generic CodeGenPrepare. Change-Id: Ib54643a0eca9c8a2aa7cc7ce38c7b296e4ca0e6e
This change makes code references not fully pc-relative. Change-Id: I829687d892b86c46ba84a24c4e93de1a21574c4c
nanoMIPS ISA does not natively support ORI/ANDI with 16-bit immediate operands. As a result, ORIs are generated incorrectly in atomic builtin expansions with the immediate value being clipped above bit 11. ANDIs may be correct if using a 3-bit register encoding, else they end up relying on GNU assemblers instruction aliases using EXT. This replaces the potentially problematic instructions with natively supported nanoMIPS instructions. Some expansions are sub-optimal on account of preferring 32-bit instructions even where 16-bit encoding is possible. Change-Id: I0f40a61e4f22a58bb91b3f11a6bd01a29452614e
Use EM_NANOMIPS for generated nanomips-elf objects Change-Id: I4e4d759c006c3f08341fdd428de2c99d0ca200b7
Change-Id: Idb31afcc5aab0ad803c54ca126d4b95e69c380a9
Use 64-bit doublewords to handle 48-bit instructions. Change-Id: I6f2c1cdd51d3de156d6013fc9b583392d7606ab6
Change-Id: Ib61ddb42057eaa631b5c4aa219ca76b291835702
Change-Id: I8a016e06544a07b80902652622a7ff41554ce306
Change-Id: I4182172fc84d9cf854cab15ebc3983ab34f804a6
Change-Id: I1404c1a21f6df683d5f1aaac36349175e89a2e23
Change-Id: Ib2bcaaee8d04aa089fd438df7c039a12ff0085f5
Change-Id: I11b042ff5d97834e69d3250548c2a1d2d1d03f6e
Change-Id: I53f986f2c8e0e5f7184c4e362e3c27934f99d7ed
Change-Id: Id68922845b03f20e040ad393abaa719ffc57f5a6
Change-Id: Ib2483ab1ad593493c88a5e7b51f157ea1ca23a88
Change-Id: I7d3653a2bd47e0d0bbfc93ccb1e74beea9e9e15e
Change-Id: I8c0c4213a7afabec7308766c7050e3fba3d0b02d
Change-Id: Ia359143068c9edbb0dfe748c3c704c0db048bd72
…stores + refactor LA_NM to ADDIUPC48_NM Change-Id: I533ac72eb3656c884b4107868db66fa2e1c3cfbf
Change-Id: Ifde8c84908318ccd4555b3001374f3972de5d0ae
Change-Id: I073a947236a401e0f1f43d634b4c069fa9a66547
Change-Id: I1f305d006273c90cb93ef8f65b626484c3859fb6
Change-Id: Ib4aae7e3c6b44d9ff326c5c282951802f8f3548f
Change-Id: I400f6f9f20d631a59730a1829b1a97223e3288fb
Providing an interface for useIntegrateAs over-rides the command-line option. Removing it allows us to control the use of integrated assembler from the command-line. Change-Id: I3326038c76e742dbbb906c39bd6f087db8cbbd96
GNU assembler supports this syntax Change-Id: Iec7fe84c7f1c50886e4edaa69f9f79489a998d72
Change-Id: I47302764c3e4005f9e7609fdf49c85f039978ecc
Change-Id: If5dc329ea6fae1a80cc58223164e598a61f4c35c
Change-Id: Ib239b18b5fe2d2e91e82dd19e31d4d4a27cf0d97
The erstwhile default which assumes that the general purpose register set is always under high pressure leads to better allocation on average than the general MIPS model which allows free allocation of up to 28 registers. Revert to earlier behaviour for now, to be looked in to along with scheduling changes. Change-Id: I2e8b04edf49552a591f4f65cd33aef652a44e88e
Change-Id: I8fee60e432e8619a79a95c1ca0142de36f242184
Change-Id: I0b36e83828d5f8641ddf70fb7b1b56c3d77235ad
Change-Id: Iea67daf6e020de023b8b6c76e60af75b2d2e49dd
The assembler dialect in the parser class is only set up when parsing assembly files. For inline assembly, it must be obtained from AsmInfo in order to correctly reflect the ISA mode. Change-Id: Iea23bcbc365fe127d1f2a0ba113db6a46012286e
Change-Id: Ic38cc32a089b7682a9cd77169e3db28ecb56667d
Inheritance structure of ParserMatchClass determines the order of instructions in MatchTable. Inherit 25-bit call operand from 10-bit call operand in order to prioritize it. This is required for balc-stubs optimization in the linker. Change-Id: I3c96d1f61862e76936e5b444bbe6280d031ed6b1
* R_NANOMIPS_TRAMP needed to inhibit stub optimization * R_NANOMIPS_NONE backend handling was missing. Added for sake of completeness. Change-Id: I3382994a7a67edc6fbe13a5ac1622934ad05da16
Change-Id: Ie09b2dc1f7041c33ba67525a3e6e59144eed5af0
Typical branch target is represented as a symbol and the assembler emits a relocation that the linker resolves to the final branch address. For immediate operands as well, we can treat the operand as a target address and emit a relocation that the linker can resolve to reach that address. This patch brings integrated assembler's handling of immediate operands in line with GNU assembler. Change-Id: Ic72fe65cb5f5617b844bd0f7ef9803be0d17d28e
* Add support for converting .shword and .sbyte data directives to R_NANOMIPS_SIGNED_[8|16] relocations. * Maps expressions with 1-bit right-shift to R_NANOMIPS_ASHIFTR_1 Change-Id: I2294313664f8eb1cfd2052f39c86e5328b0648d5
* Parse and ignore .jumptable directive * Parse and ignore R_NANOMIPS_JUMPTABLE_LOAD relocation This is to facilitate the compiler to enable jump-table compression regardless of whether it uses integrated or external assembler. It does not have any impact on object encoding generated by integrated assembler, but allows the same generated assembly to be handled by either assemblers. Change-Id: I8f9ed12c7acf5cef11fada62f230ce92cd363750
Native MTTR/MFTR instructions should only accept COP registers, that is simple numbered registers as the second operand. Translate the incoming registers from the aliases to the correct format. Change-Id: I778f374feff3ea9022905314c0c2e262b1909f3c
* Disable linker relaxation by default to match GNU assembler * Disable PC-relative addressing by default to match GNU assembler * Don't emit directives to enable PC-relative addressing and linker relaxations unconditionally in assembly file. Instead check subtarget features to decide when these must be enabled. * Test-suite updates to match new defaults Change-Id: I54f32c77edd7f8ef0352bc6e87ec86ca7c4cec02
* Use cc1as as the external assembler when compiling LTO with -fintegrated-as * When using nanomips-elf-as as external assembler for LTO, pass option -mlegacyregs to work around different MTTR/MFTR operand constraints. Change-Id: Ic2540162637dfa76cfe243ac3ab127e259f0e9a9
Change-Id: Iec6ed1c300c3ce19299d7f8a1005f4df060573d8
Fixup nanoMIPS Register Re-allocation name in IR prints (bug llvm#94) Change-Id: Iac2c85d52a68c6f21781ee77833af9f04d44bded
Change-Id: Icbbd8f7abf2910698b07439a84a0b15e91653a09
draganmladjenovic
requested review from
cme,
djtodoro,
farazs-github and
milica-lazarevic
|
Abandoned in favor of gerrit PR. |
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