Change-Id: Icd1b11638dcca6ebe65db5cf44698e4038d34891

This reverts commit 0853501.

Change-Id: I4d1b41912d770abf4a6cc85e163f078be1cb91f1

... by reusing existing offset in CodeGenPrepare.

Added NanoMipsCodeGenPrepare pass witch munges constant geps into
a form that later can be optimized by generic CodeGenPrepare.

Change-Id: Ib54643a0eca9c8a2aa7cc7ce38c7b296e4ca0e6e

This change makes code references not fully pc-relative.

Change-Id: I829687d892b86c46ba84a24c4e93de1a21574c4c

nanoMIPS ISA does not natively support ORI/ANDI with 16-bit immediate
operands. As a result, ORIs are generated incorrectly in atomic
builtin expansions with the immediate value being clipped above
bit 11. ANDIs may be correct if using a 3-bit register encoding, else
they end up relying on GNU assemblers instruction aliases using EXT.

This replaces the potentially problematic instructions with
natively supported nanoMIPS instructions. Some expansions are
sub-optimal on account of preferring 32-bit instructions even
where 16-bit encoding is possible.

Change-Id: I0f40a61e4f22a58bb91b3f11a6bd01a29452614e

Use EM_NANOMIPS for generated nanomips-elf objects

Change-Id: I4e4d759c006c3f08341fdd428de2c99d0ca200b7

Change-Id: Idb31afcc5aab0ad803c54ca126d4b95e69c380a9

Use 64-bit doublewords to handle 48-bit instructions.

Change-Id: I6f2c1cdd51d3de156d6013fc9b583392d7606ab6

Change-Id: Ib61ddb42057eaa631b5c4aa219ca76b291835702

Change-Id: I8a016e06544a07b80902652622a7ff41554ce306

Change-Id: I4182172fc84d9cf854cab15ebc3983ab34f804a6

Change-Id: I1404c1a21f6df683d5f1aaac36349175e89a2e23

Change-Id: Ib2bcaaee8d04aa089fd438df7c039a12ff0085f5

Change-Id: I11b042ff5d97834e69d3250548c2a1d2d1d03f6e

Change-Id: I53f986f2c8e0e5f7184c4e362e3c27934f99d7ed

Change-Id: Id68922845b03f20e040ad393abaa719ffc57f5a6

Change-Id: Ib2483ab1ad593493c88a5e7b51f157ea1ca23a88

Change-Id: I7d3653a2bd47e0d0bbfc93ccb1e74beea9e9e15e

Change-Id: I8c0c4213a7afabec7308766c7050e3fba3d0b02d

Change-Id: Ia359143068c9edbb0dfe748c3c704c0db048bd72

…stores + refactor LA_NM to ADDIUPC48_NM

Change-Id: I533ac72eb3656c884b4107868db66fa2e1c3cfbf

Change-Id: Ifde8c84908318ccd4555b3001374f3972de5d0ae

Change-Id: I073a947236a401e0f1f43d634b4c069fa9a66547

Change-Id: I1f305d006273c90cb93ef8f65b626484c3859fb6

Change-Id: Ib4aae7e3c6b44d9ff326c5c282951802f8f3548f

Change-Id: I400f6f9f20d631a59730a1829b1a97223e3288fb

Providing an interface for useIntegrateAs over-rides
the command-line option. Removing it allows us to control
the use of integrated assembler from the command-line.

Change-Id: I3326038c76e742dbbb906c39bd6f087db8cbbd96

Change-Id: If266770310433045e0c1ac1aeb3231b4c13529fc

Change-Id: I24dce47606295142ebffba781aa1ab09293063ef

Change-Id: I9231ab0e866ed87927a28e9dc605d1cf5ff9c64c

Change-Id: Ic00423166d7c5ca66a1abe1326dccb9bd5e4921c

This fixes simple label differences as required for exception
tables and debug-info, but not the diff+shift cases used by
jumptable optimization.

Change-Id: I799514cb94b17cb2436643fa44c4060c9023e8c3

Change-Id: Ib905ba29411a4af672c088c3b86aa4a686cc00f0

Change-Id: I191c4a236ba923b1e166fd4595e4a8a7711c092f

Remove DAG patterns for instructions that use a restricted register set.

Change-Id: I5ce746e8927fa5520ca5cfa714e05fb08938926c

* Fix build warnings due to patchset 3
* add ALIGN instruction alias
* add TwoOperandAlias 
* Add pattern for NOT as NOR
* Fix 2 operand constraints for 3-register arithmetic
* Add aliases for ADDIU as ADDU and ORI as OR
* Missing ADDIUNEG opcode in PC-relative instruction generation
* Limit pointer arithmetic to ADDIU[48]

Change-Id: I9f64baa02081302a33344af0afdb7e652d453faf

Change-Id: Ia91f95859cab10d780275239ffefe6a85d918875

In the absence of an instruction compression pass or mechanism,
compression for NanoMips is mediated by the assembly matcher
finding the shortest instructions for a base mnemonic. This
requires the compilation actions to go through a distinct assembly
step, similar to the -via-file-asm option.

Change-Id: I6eec5bed1bff1965d58578ed8624176df2c71d4f

Change-Id: I2cdddbab8c43b725fe1964b7c2f2cd4d6e542528

Change-Id: I70fa500367d372b1af0c47f875b673062cc6af1c

Change-Id: I2fbdb326bd20cba3a8fd825dd1f7f7291c34436e

nanoMIPS mnemonics can have an optional architectural suffix to
disambiguate multiple instructions which have the same mnemonic.
As per the ISA, this suffix is enclosed in square brackets, for
example: li[48]. The assembly parser must tokenize the suffix
along with the mnemonic as one token.

Change-Id: I240d7de279800650c6b36600a8bbfd83559ae4d5

Change-Id: I2dbd5e00ce450cf966f60d836a9b42ff954925d5

Change-Id: If77b00b39437aeb736603f0de240613aec52594d

Change-Id: Ifa98c5c333b9f332a9c8c5aed824c3fefdeb2036

GNU assembler supports this syntax

Change-Id: Iec7fe84c7f1c50886e4edaa69f9f79489a998d72

Change-Id: I47302764c3e4005f9e7609fdf49c85f039978ecc

Change-Id: If5dc329ea6fae1a80cc58223164e598a61f4c35c

Change-Id: Ib239b18b5fe2d2e91e82dd19e31d4d4a27cf0d97

The erstwhile default which assumes that the general purpose register
set is always under high pressure leads to better allocation on
average than the general MIPS model which allows free allocation of
up to 28 registers.  Revert to earlier behaviour for now, to be looked
in to along with scheduling changes.

Change-Id: I2e8b04edf49552a591f4f65cd33aef652a44e88e

Change-Id: I8fee60e432e8619a79a95c1ca0142de36f242184

Change-Id: I0b36e83828d5f8641ddf70fb7b1b56c3d77235ad

Change-Id: Iea67daf6e020de023b8b6c76e60af75b2d2e49dd

The assembler dialect in the parser class is only set up when parsing
assembly files.  For inline assembly, it must be obtained from
AsmInfo in order to correctly reflect the ISA mode.

Change-Id: Iea23bcbc365fe127d1f2a0ba113db6a46012286e

Change-Id: Ic38cc32a089b7682a9cd77169e3db28ecb56667d

Inheritance structure of ParserMatchClass determines the order of
instructions in MatchTable.  Inherit 25-bit call operand from
10-bit call operand in order to prioritize it.

This is required for balc-stubs optimization in the linker.

Change-Id: I3c96d1f61862e76936e5b444bbe6280d031ed6b1

* R_NANOMIPS_TRAMP needed to inhibit stub optimization
* R_NANOMIPS_NONE backend handling was missing. Added for sake of completeness.

Change-Id: I3382994a7a67edc6fbe13a5ac1622934ad05da16

Change-Id: Ie09b2dc1f7041c33ba67525a3e6e59144eed5af0

Typical branch target is represented as a symbol and the assembler
emits a relocation that the linker resolves to the final branch
address. For immediate operands as well, we can treat the operand as
a target address and emit a relocation that the linker can resolve
to reach that address. This patch brings integrated assembler's
handling of immediate operands in line with GNU assembler.

Change-Id: Ic72fe65cb5f5617b844bd0f7ef9803be0d17d28e

* Add support for converting .shword and .sbyte data directives
to R_NANOMIPS_SIGNED_[8|16] relocations.
* Maps expressions with 1-bit right-shift to R_NANOMIPS_ASHIFTR_1

Change-Id: I2294313664f8eb1cfd2052f39c86e5328b0648d5

* Parse and ignore .jumptable directive
* Parse and ignore R_NANOMIPS_JUMPTABLE_LOAD relocation

This is to facilitate the compiler to enable jump-table compression
regardless of whether it uses integrated or external assembler. It does
not have any impact on object encoding generated by integrated assembler,
but allows the same generated assembly to be handled by either assemblers.

Change-Id: I8f9ed12c7acf5cef11fada62f230ce92cd363750

Native MTTR/MFTR instructions should only accept COP registers, that
is simple numbered registers as the second operand.  Translate the
incoming registers from the aliases to the correct format.

Change-Id: I778f374feff3ea9022905314c0c2e262b1909f3c

* Disable linker relaxation by default to match GNU assembler
* Disable PC-relative addressing by default to match GNU assembler
* Don't emit directives to enable PC-relative addressing and linker
relaxations unconditionally in assembly file. Instead check subtarget
features to decide when these must be enabled.
* Test-suite updates to match new defaults

Change-Id: I54f32c77edd7f8ef0352bc6e87ec86ca7c4cec02

* Use cc1as as the external assembler when compiling LTO with -fintegrated-as

* When using nanomips-elf-as as external assembler for LTO, pass option
-mlegacyregs to work around different MTTR/MFTR operand constraints.

Change-Id: Ic2540162637dfa76cfe243ac3ab127e259f0e9a9

Change-Id: Iec6ed1c300c3ce19299d7f8a1005f4df060573d8

Fixup nanoMIPS Register Re-allocation name in IR prints (bug llvm#94)

Change-Id: Iac2c85d52a68c6f21781ee77833af9f04d44bded

Change-Id: Icbbd8f7abf2910698b07439a84a0b15e91653a09