32-bit 5-stage Pipeline MIPS Processor FPGA

• With early branch determination in decode stage, and hazard unit handling stall and data forwarding logic.
• Memory mapped factorial accelerator and GPIO wrapper.
• Developed in Xilinx Vivado 2019.2 and tested on the Basys 3 Artix-7 FPGA Trainer Board.
• To open Vivaldo project, run the create_project.tcl TCL script in Vivaldo

Pipline datapath

System integration