Update the clock gating primitive for VCS (#169)

OpenXiangShan · Mar 20, 2024 · fdd56a5 · fdd56a5
1 parent a4b0c8a
commit fdd56a5
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/src/main/resources/STD_CLKGT_func.v b/src/main/resources/STD_CLKGT_func.v
@@ -10,6 +10,12 @@ module STD_CLKGT_func (
 
   assign clk_en = E | TE;
 
+`ifdef VCS
+  always @(CK or clk_en) begin
+    if (CK == 1'b0)
+      clk_en_reg <= clk_en;
+  end
+`else
 `ifdef VERILATOR_5
   always @(CK or clk_en) begin
     if (CK == 1'b0)
@@ -20,6 +26,7 @@ module STD_CLKGT_func (
     begin
       clk_en_reg = clk_en;
     end
+`endif
 `endif
 
   assign Q = CK & clk_en_reg;