Merge branch 'master' into master

.github/workflows/main.yml

@@ -22,7 +22,7 @@ jobs:
       - name: Compile
         run: |
           mill -i design[3.6.0].compile
-          mill -i design[6.0.0].compile
+          mill -i design[6.1.0].compile
 
       - name: Generate Verilog
         run: |
@@ -319,8 +319,9 @@ jobs:
             make simv DIFFTEST_PERFCNT=1 VCS=verilator -j2
             ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000
             ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so
+            cd difftest && git restore src
 
-      - name: Verilator Build with VCS Top (with Squash DutZone Batch and Global Enable PerfCnt)
+      - name: Verilator Build with VCS Top (with GlobalEnable DutZone Squash SquashReplay Batch PerfCnt)
         run: |
             cd $GITHUB_WORKSPACE/../xs-env
             source ./env.sh
@@ -329,11 +330,13 @@ jobs:
             make clean
             sed -i 's/isSquash: Boolean = false/isSquash: Boolean = true/' difftest/src/main/scala/Gateway.scala
             sed -i 's/hasDutZone: Boolean = false/hasDutZone: Boolean = true/' difftest/src/main/scala/Gateway.scala
+            sed -i 's/squashReplay: Boolean = false/squashReplay: Boolean = true/' difftest/src/main/scala/Gateway.scala
             sed -i 's/isBatch: Boolean = false/isBatch: Boolean = true/' difftest/src/main/scala/Gateway.scala
             sed -i 's/hasGlobalEnable: Boolean = false/hasGlobalEnable: Boolean = true/' difftest/src/main/scala/Gateway.scala
             make simv DIFFTEST_PERFCNT=1 VCS=verilator -j2
             ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000
             ./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so
+            cd difftest && git restore src
 
       - name: Verilator Build with VCS Top (with workload-list)
         run : |

.mill-version

@@ -1,2 +1 @@
-0.11.1
-
+0.11.6

build.sc

@@ -22,7 +22,7 @@ object ivys {
   val scala = "2.13.10"
   val chiselCrossVersions = Map(
     "3.6.0" -> (ivy"edu.berkeley.cs::chisel3:3.6.0", ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0"),
-    "6.0.0" -> (ivy"org.chipsalliance::chisel:6.0.0", ivy"org.chipsalliance:::chisel-plugin:6.0.0"),
+    "6.1.0" -> (ivy"org.chipsalliance::chisel:6.1.0", ivy"org.chipsalliance:::chisel-plugin:6.1.0"),
   )
 }
 

config/config.h

@@ -113,6 +113,11 @@ extern unsigned long EMU_FLASH_SIZE;
 // whether to check l2tlb response
 // #define DEBUG_L2TLB
 
+// whether to enable REF/GoldenMemory record origin data of memory and restore
+#ifdef CONFIG_DIFFTEST_SQUASH_REPLAY
+#define ENABLE_STORE_LOG
+#endif // CONFIG_DIFFTEST_SQUASH_REPLAY
+
 // -----------------------------------------------------------------------
 // Simulator run ahead config
 // -----------------------------------------------------------------------

src/test/csrc/difftest/difftest.cpp

@@ -161,8 +161,8 @@ Difftest::~Difftest() {
   }
 #ifdef CONFIG_DIFFTEST_SQUASH_REPLAY
   free(state_ss);
-  if (proxy_ss) {
-    free(proxy_ss);
+  if (proxy_reg_ss) {
+    free(proxy_reg_ss);
   }
 #endif // CONFIG_DIFFTEST_SQUASH_REPLAY
 }
@@ -186,19 +186,23 @@ bool Difftest::squash_check() {
 
 void Difftest::squash_snapshot() {
   memcpy(state_ss, state, sizeof(DiffState));
-  memcpy(proxy_ss, proxy, sizeof(REF_PROXY));
+  memcpy(proxy_reg_ss, &proxy->regs_int, proxy_reg_size);
   proxy->ref_csrcpy(squash_csr_buf, REF_TO_DUT);
-  proxy->ref_memcpy(PMEM_BASE, squash_membuf, squash_memsize, REF_TO_DUT);
+  proxy->ref_store_log_reset();
+  proxy->set_store_log(true);
+  goldenmem_store_log_reset();
+  goldenmem_set_store_log(true);
 }
 
 void Difftest::squash_replay() {
   inReplay = true;
   replay_idx = squash_idx;
   memcpy(state, state_ss, sizeof(DiffState));
-  memcpy(proxy, proxy_ss, sizeof(REF_PROXY));
+  memcpy(&proxy->regs_int, proxy_reg_ss, proxy_reg_size);
   proxy->ref_regcpy(&proxy->regs_int, DUT_TO_REF, false);
   proxy->ref_csrcpy(squash_csr_buf, DUT_TO_REF);
-  proxy->ref_memcpy(PMEM_BASE, squash_membuf, squash_memsize, DUT_TO_REF);
+  proxy->ref_store_log_restore();
+  goldenmem_store_log_restore();
   difftest_squash_replay(replay_idx);
 }
 #endif // CONFIG_DIFFTEST_SQUASH_REPLAY
@@ -215,6 +219,9 @@ int Difftest::step() {
   isSquash = squash_check();
   if (isSquash) {
     squash_snapshot();
+  } else {
+    proxy->set_store_log(false);
+    goldenmem_set_store_log(false);
   }
 #endif // CONFIG_DIFFTEST_SQUASH_REPLAY
 

src/test/csrc/difftest/difftest.h

@@ -380,10 +380,9 @@ class Difftest {
   int replay_idx;
 
   DiffState *state_ss = NULL;
-  REF_PROXY *proxy_ss = NULL;
+  int proxy_reg_size = 0;
+  uint8_t *proxy_reg_ss = NULL;
   uint64_t squash_csr_buf[4096];
-  long squash_memsize;
-  char *squash_membuf;
   bool squash_check();
   void squash_snapshot();
   void squash_replay();

src/test/csrc/difftest/goldenmem.h

@@ -45,4 +45,9 @@ void paddr_write(uint64_t addr, word_t data, int len);
 bool is_sfence_safe(uint64_t addr, int len);
 bool in_pmem(uint64_t addr);
 
+#ifdef ENABLE_STORE_LOG
+void goldenmem_set_store_log(bool enable);
+void goldenmem_store_log_reset();
+void goldenmem_store_log_restore();
+#endif
 #endif

src/test/csrc/difftest/refproxy.cpp

@@ -77,6 +77,11 @@ AbstractRefProxy::AbstractRefProxy(int coreid, size_t ram_size, const char *env,
     ref_set_ramsize(ram_size);
   }
 
+#ifdef ENABLE_STORE_LOG
+  check_and_assert(ref_store_log_reset);
+  check_and_assert(ref_store_log_restore);
+#endif // ENABLE_STORE_LOG
+
   ref_init();
 }
 

src/test/csrc/difftest/refproxy.h

@@ -74,6 +74,7 @@ class RefProxyConfig {
 public:
   bool ignore_illegal_mem_access = false;
   bool debug_difftest = false;
+  bool enable_store_log = false;
 };
 
 /* clang-format off */
@@ -115,6 +116,7 @@ class RefProxyConfig {
 #define REF_ALL(f)  \
   REF_BASE(f)       \
   REF_RUN_AHEAD(f)  \
+  REF_STORE_LOG(f)  \
   REF_DEBUG_MODE(f)
 
 #define REF_OPTIONAL(f)                                                       \