Update README.md

README.md

@@ -27,12 +27,13 @@ import $file.difftest.build
 
 // We recommend using a fixed Chisel version.
 object difftest extends millbuild.difftest.build.CommonDiffTest {
-  def crossValue: String = "3.5.6"
+  def crossValue: String = "3.6.0"
 
   override def millSourcePath = os.pwd / "difftest"
 }
 
-// This is for advanced users only. All supported Chisel versions are listed in `build.sc`.
+// This is for advanced users only.
+// All supported Chisel versions are listed in `build.sc`.
 // To pass a cross value to difftest:
 object difftest extends Cross[millbuild.difftest.build.CommonDiffTest](chiselVersions) {
   override def millSourcePath = os.pwd / "difftest"
@@ -46,6 +47,8 @@ emu: sim-verilog
 ```
 
 2. Add difftest modules (in Chisel or Verilog) to your design.
+All modules have been listed in the [APIs](#apis) chapter. Some of them are optional.
+
 ```scala
 import difftest._
 
@@ -60,7 +63,7 @@ difftest.wdest  := io.wb.rfDest
 difftest.wpdest := io.wb.rfDest
 ```
 
-3. Call `val difftesst = DifftestModule.finish(cpu: String)` at the top module whose name should be `SimTop`. The variable name `difftest` must be used to ensure DiffTest could capture the input signals.
+3. Call `val difftesst = DifftestModule.finish(cpu: String)` at the top module whose module name should be `SimTop`. The variable name `difftest` must be used to ensure DiffTest could capture the input signals.
 
 An optional UART input/output can be connected to DiffTest. DiffTest will automatically DontCare it internally.
 
@@ -80,6 +83,8 @@ We provide example designs, including:
 - [NutShell](https://github.com/OSCPU/NutShell/tree/dev-difftest)
 - [Rocket](https://github.com/OpenXiangShan/rocket-chip/tree/dev-difftest)
 
+If you encountered any issues when integrating DiffTest to your own design, feel free to let us know with necessary information on how you have modified your design. We will try our best to assist you.
+
 ## APIs
 
 Currently we are supporting the RISC-V base ISA as well as some extensions,
@@ -111,6 +116,8 @@ coherence via RefillTest.
 | `DiffLrScEvent` | Executed LR/SC instructions | No |
 
 The DiffTest framework comes with a simulation framework with some top-level IOs.
+They will be automatically created when calling `DifftestModule.finish(cpu: String)`.
+
 * `LogCtrlIO`
 * `PerfCtrlIO`
 * `UARTIO`
@@ -139,4 +146,4 @@ Please set the correct parameters for the interfaces.
 # Further reference
 
 * [Difftest: detailed usage (Chinese)](./doc/usage.md)
-* [SMP-Difftest 支持多处理器的差分测试方法](https://github.com/OpenXiangShan/XiangShan-doc/blob/main/slides/20210624-RVWC-SMP-Difftest%20%E6%94%AF%E6%8C%81%E5%A4%9A%E5%A4%84%E7%90%86%E5%99%A8%E7%9A%84%E5%B7%AE%E5%88%86%E6%B5%8B%E8%AF%95%E6%96%B9%E6%B3%95.pdf)
+* [SMP-Difftest 支持多处理器的差分测试方法](https://github.com/OpenXiangShan/XiangShan-doc/blob/main/slides/20210624-RVWC-SMP-Difftest%20%E6%94%AF%E6%8C%81%E5%A4%9A%E5%A4%84%E7%90%86%E5%99%A8%E7%9A%84%E5%B7%AE%E5%88%86%E6%B5%8B%E8%AF%95%E6%96%B9%E6%B3%95.pdf)