Bump Mill 0.11.6 and Chisel 6.1.0

OpenXiangShan · Feb 26, 2024 · c9ebf22 · c9ebf22
1 parent b4d9e66
commit c9ebf22
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Showing 3 changed files with 3 additions and 4 deletions.
diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
@@ -22,7 +22,7 @@ jobs:
       - name: Compile
         run: |
           mill -i design[3.6.0].compile
-          mill -i design[6.0.0].compile
+          mill -i design[6.1.0].compile
 
       - name: Generate Verilog
         run: |

diff --git a/.mill-version b/.mill-version
@@ -1,2 +1 @@
-0.11.1
-
+0.11.6
diff --git a/build.sc b/build.sc
@@ -22,7 +22,7 @@ object ivys {
   val scala = "2.13.10"
   val chiselCrossVersions = Map(
     "3.6.0" -> (ivy"edu.berkeley.cs::chisel3:3.6.0", ivy"edu.berkeley.cs:::chisel3-plugin:3.6.0"),
-    "6.0.0" -> (ivy"org.chipsalliance::chisel:6.0.0", ivy"org.chipsalliance:::chisel-plugin:6.0.0"),
+    "6.1.0" -> (ivy"org.chipsalliance::chisel:6.1.0", ivy"org.chipsalliance:::chisel-plugin:6.1.0"),
   )
 }