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Add built-in Perf for difftest
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We will dump built-in Perf for difftest at the end of simulation.
These printfs can be controled by difftest_perfCtrl_dump.

For emu, we call Emulator::trigger_stat_dump. For simv, we raise
difftest_perfCtrl_dump when simv_result is not zero.

We add system task decl $fwrite to Palladium scripts, otherwise it
will be ignored automatically.
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klin02 committed Mar 19, 2024
1 parent 965fcd3 commit e5f67d9
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Showing 6 changed files with 36 additions and 8 deletions.
8 changes: 4 additions & 4 deletions .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -304,7 +304,7 @@ jobs:
cd $GITHUB_WORKSPACE/../xs-env/NutShell
source ./env.sh
make clean
make simv MILL_ARGS="--difftest-config Z" DIFFTEST_PERFCNT=1 VCS=verilator -j2
make simv MILL_ARGS="--difftest-config ZP" DIFFTEST_PERFCNT=1 VCS=verilator -j2
./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000
./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so
Expand All @@ -315,7 +315,7 @@ jobs:
cd $GITHUB_WORKSPACE/../xs-env/NutShell
source ./env.sh
make clean
make simv MILL_ARGS="--difftest-config BI" DIFFTEST_PERFCNT=1 VCS=verilator -j2
make simv MILL_ARGS="--difftest-config BIP" DIFFTEST_PERFCNT=1 VCS=verilator -j2
./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000
./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so
Expand All @@ -326,7 +326,7 @@ jobs:
cd $GITHUB_WORKSPACE/../xs-env/NutShell
source ./env.sh
make clean
make simv MILL_ARGS="--difftest-config ZESRB" DIFFTEST_PERFCNT=1 VCS=verilator -j2
make simv MILL_ARGS="--difftest-config ZESRBP" DIFFTEST_PERFCNT=1 VCS=verilator -j2
./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000
./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so
Expand All @@ -337,7 +337,7 @@ jobs:
cd $GITHUB_WORKSPACE/../xs-env/NutShell
source ./env.sh
make clean
make simv MILL_ARGS="--difftest-config ESRBIN" DIFFTEST_PERFCNT=1 VCS=verilator -j2
make simv MILL_ARGS="--difftest-config ESRBINP" DIFFTEST_PERFCNT=1 VCS=verilator -j2
./build/simv +workload=./ready-to-run/microbench.bin +e=0 +no-diff +max-cycles=100000
./build/simv +workload=./ready-to-run/microbench.bin +e=0 +diff=./ready-to-run/riscv64-nemu-interpreter-so
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1 change: 1 addition & 0 deletions scripts/palladium/argConfigs.qel
Original file line number Diff line number Diff line change
Expand Up @@ -2,3 +2,4 @@
* $value$plusargs TB_IMPORT
* $finish TB_IMPORT
* $random TB_IMPORT
* $fwrite GFIFO
14 changes: 11 additions & 3 deletions src/main/scala/Batch.scala
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@ import chisel3._
import chisel3.util._
import difftest._
import difftest.gateway.GatewayConfig
import difftest.common.DifftestPerf

class BatchIO(dataType: UInt, infoType: UInt) extends Bundle {
val data = dataType
Expand Down Expand Up @@ -131,9 +132,16 @@ class BatchEndpoint(template: Seq[DifftestBundle], bundles: Seq[DifftestBundle],
val state_info_len = RegInit(0.U(MaxInfoByteWidth.W))
val state_step_cnt = RegInit(0.U(log2Ceil(config.batchSize + 1).W))

val exceed = (state_data_len +& step_data_len > MaxDataByteLen.U) |
(state_info_len +& step_info_len + (infoWidth / 8).U > MaxInfoByteLen.U)
val should_tick = delayed_enable && (exceed || state_step_cnt === config.batchSize.U)
val data_exceed = state_data_len +& step_data_len > MaxDataByteLen.U
val info_exceed = state_info_len +& step_info_len + (infoWidth / 8).U > MaxInfoByteLen.U
val step_exceed = state_step_cnt === config.batchSize.U
if (config.hasBuiltInPerf) {
DifftestPerf("BatchExceed_data", data_exceed.asUInt)
DifftestPerf("BatchExceed_info", info_exceed.asUInt)
DifftestPerf("BatchExceed_step", step_exceed.asUInt)
}

val should_tick = delayed_enable && (data_exceed | info_exceed | step_exceed)
when(delayed_enable) {
when(should_tick) {
state_data := step_data
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2 changes: 2 additions & 0 deletions src/main/scala/Gateway.scala
Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,7 @@ case class GatewayConfig(
batchSize: Int = 32,
hasInternalStep: Boolean = false,
isNonBlock: Boolean = false,
hasBuiltInPerf: Boolean = false,
) {
def dutZoneSize: Int = if (hasDutZone) 2 else 1
def dutZoneWidth: Int = log2Ceil(dutZoneSize)
Expand Down Expand Up @@ -105,6 +106,7 @@ object Gateway {
case 'B' => config = config.copy(isBatch = true)
case 'I' => config = config.copy(hasInternalStep = true)
case 'N' => config = config.copy(isNonBlock = true)
case 'P' => config = config.copy(hasBuiltInPerf = true)
case x => println(s"Unknown Gateway Config $x")
}
config.check()
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12 changes: 12 additions & 0 deletions src/main/scala/common/LogPerfControl.scala
Original file line number Diff line number Diff line change
Expand Up @@ -61,3 +61,15 @@ object LogPerfControl {

def apply(): LogPerfControl = instances.find(_.isVisible).getOrElse(instantiate())
}

object DifftestPerf {
def apply(perfName: String, perfCnt: UInt) = {
val helper = LogPerfControl.apply()
val counter = RegInit(0.U(64.W))
val next_counter = WireInit(counter + perfCnt)
counter := Mux(helper.clean, 0.U, next_counter)
when(helper.dump) {
printf(p"[DIFFTEST_PERF][time=${helper.timer}] $perfName, $next_counter\n")
}
}
}
7 changes: 6 additions & 1 deletion src/test/vsrc/vcs/top.v
Original file line number Diff line number Diff line change
Expand Up @@ -213,7 +213,6 @@ SimTop sim(

assign difftest_logCtrl_level = 0;
assign difftest_perfCtrl_clean = 0;
assign difftest_perfCtrl_dump = 0;
assign difftest_uart_in_ch = 8'hff;

always @(posedge clock) begin
Expand Down Expand Up @@ -244,6 +243,12 @@ assign workload_switch = simv_result == `SIMV_DONE;
`endif // ENABLE_WORKLOAD_SWITCH
`endif // TB_NO_DPIC

`ifndef TB_NO_DPIC
assign difftest_perfCtrl_dump = simv_result != 0;
`else
assign difftest_perfCtrl_dump = 0;
`endif // TB_NO_DPIC

reg [63:0] n_cycles;
always @(posedge clock) begin
if (reset) begin
Expand Down

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