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difftest: The difftest remove redundant logic gates #504

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difftest: The difftest remove redundant logic gates #504

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8 changes: 4 additions & 4 deletions src/main/scala/Batch.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -210,8 +210,8 @@ class BatchCollector(

val data_site = WireInit(0.U((alignWidth * length).W))
data_site := VecInit(delay_data.zipWithIndex.map { case (d, idx) =>
val offset = if (idx == 0) 0.U else MuxLookup(PopCount(delay_valid.take(idx)), 0.U)(offset_map)
Mux(delay_valid(idx), (d << offset).asUInt, 0.U)
val offset = MuxLookup(PopCount(delay_valid.take(idx)), 0.U)(offset_map)
Mux(idx.U === 0.U, (d << offset).asUInt, 0.U)
}.toSeq).reduce(_ | _)

when(delay_valid.asUInt.orR) {
Expand Down Expand Up @@ -314,8 +314,8 @@ class BatchAssembler(
}
// Flush state to provide more space for peak data
val state_flush = enable && step_stats_vec.last.data_len > param.MaxDataByteLen.U
val timeout_count = RegInit(0.U(32.W))
val timeout = timeout_count === 200000.U
val timeout_count = RegInit(0.U(18.W))
val timeout = timeout_count === 0x3ffff.U
if (config.hasBuiltInPerf) {
DifftestPerf("BatchExceed_data", data_exceed_vec.asUInt.orR)
DifftestPerf("BatchExceed_info", info_exceed_vec.asUInt.orR)
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/Squash.scala
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Expand Up @@ -103,8 +103,8 @@ class SquashEndpoint(bundles: Seq[Valid[DifftestBundle]], config: GatewayConfig)
.filter(_.desiredCppName == "trace_info")
.map(_.asInstanceOf[DiffTraceInfo].in_replay)
.foldLeft(false.B)(_ || _)
val timeout_count = RegInit(0.U(32.W))
val timeout = timeout_count === 200000.U
val timeout_count = RegInit(0.U(18.W))
val timeout = timeout_count === 0x3ffff.U
val global_tick = !control.enable || in_replay || timeout

val uniqBundles = bundles.map(_.bits).distinctBy(_.desiredCppName)
Expand Down