update(cherryusb): update to v1.5.0

bsp/bouffalo_lab/bl61x/board/Kconfig

@@ -33,23 +33,17 @@ menuconfig BSP_USING_USB
     default n
     if BSP_USING_USB
         config BSP_USING_USB_DEVICE
-            bool "Enable USB Device, default is msc ramdisk"
+            bool "Enable USB Device"
             default n
             select RT_USING_CHERRYUSB
             select RT_CHERRYUSB_DEVICE
             select RT_CHERRYUSB_DEVICE_SPEED_HS
             select RT_CHERRYUSB_DEVICE_BL
-            select RT_CHERRYUSB_DEVICE_MSC
-            select RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
         config BSP_USING_USB_HOST
             bool "Enable USB Host"
             default n
             select RT_USING_CACHE
             select RT_USING_CHERRYUSB
             select RT_CHERRYUSB_HOST
             select RT_CHERRYUSB_HOST_EHCI_BL
-            select RT_CHERRYUSB_HOST_CDC_ACM
-            select RT_CHERRYUSB_HOST_HID
-            select RT_CHERRYUSB_HOST_MSC
-            select RT_CHERRYUSB_HOST_CDC_RNDIS
     endif

bsp/bouffalo_lab/bl61x/board/usb_config.h

@@ -6,11 +6,15 @@
 #ifndef CHERRYUSB_CONFIG_H
 #define CHERRYUSB_CONFIG_H
 
-#include <rtthread.h>
-
 /* ================ USB common Configuration ================ */
 
+#ifdef __RTTHREAD__
+#include <rtthread.h>
+
 #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__)
+#else
+#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
+#endif
 
 #ifndef CONFIG_USB_DBG_LEVEL
 #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
@@ -19,14 +23,23 @@
 /* Enable print with color */
 #define CONFIG_USB_PRINTF_COLOR_ENABLE
 
-/* data align size when use dma */
-#ifndef CONFIG_USB_ALIGN_SIZE
+#define CONFIG_USB_DCACHE_ENABLE
+
+/* data align size when use dma or use dcache */
+#ifdef CONFIG_USB_DCACHE_ENABLE
+#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64
+#else
 #define CONFIG_USB_ALIGN_SIZE 4
 #endif
 
 /* attribute data into no cache ram */
 #define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
 
+/* use usb_memcpy default for high performance but cost more flash memory.
+ * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
+*/
+// #define CONFIG_USB_MEMCPY_DISABLE
+
 /* ================= USB Device Stack Configuration ================ */
 
 /* Ep0 in and out transfer buffer */
@@ -48,6 +61,20 @@
 /* Enable test mode */
 // #define CONFIG_USBDEV_TEST_MODE
 
+/* enable advance desc register api */
+#define CONFIG_USBDEV_ADVANCE_DESC
+
+/* move ep0 setup handler from isr to thread */
+// #define CONFIG_USBDEV_EP0_THREAD
+
+#ifndef CONFIG_USBDEV_EP0_PRIO
+#define CONFIG_USBDEV_EP0_PRIO 4
+#endif
+
+#ifndef CONFIG_USBDEV_EP0_STACKSIZE
+#define CONFIG_USBDEV_EP0_STACKSIZE 2048
+#endif
+
 #ifndef CONFIG_USBDEV_MSC_MAX_LUN
 #define CONFIG_USBDEV_MSC_MAX_LUN 1
 #endif
@@ -82,6 +109,28 @@
 #define CONFIG_USBDEV_MSC_STACKSIZE 2048
 #endif
 
+#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE
+#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS
+#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME
+#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256
+#endif
+
+#define CONFIG_USBDEV_MTP_THREAD
+
+#ifndef CONFIG_USBDEV_MTP_PRIO
+#define CONFIG_USBDEV_MTP_PRIO 4
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_STACKSIZE
+#define CONFIG_USBDEV_MTP_STACKSIZE 4096
+#endif
+
 #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
 #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
 #endif
@@ -100,6 +149,7 @@
 #endif
 
 #define CONFIG_USBDEV_RNDIS_USING_LWIP
+#define CONFIG_USBDEV_CDC_ECM_USING_LWIP
 
 /* ================ USB HOST Stack Configuration ================== */
 
@@ -210,6 +260,11 @@
 #define CONFIG_USBDEV_EP_NUM 5
 #endif
 
+// #define CONFIG_USBDEV_SOF_ENABLE
+
+/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */
+#define CONFIG_USB_HS
+
 /* ---------------- FSDEV Configuration ---------------- */
 //#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
 
@@ -220,7 +275,7 @@
 // #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
 /* IN Endpoints Max packet Size / 4 */
 // #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
-// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
+// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4)
 // #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
 // #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
 // #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
@@ -229,6 +284,8 @@
 // #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
 // #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
 
+// #define CONFIG_USB_DWC2_DMA_ENABLE
+
 /* ---------------- MUSB Configuration ---------------- */
 // #define CONFIG_USB_MUSB_SUNXI
 
@@ -246,15 +303,19 @@
 #define CONFIG_USB_EHCI_HCCR_OFFSET     (0x0)
 #define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
 #define CONFIG_USB_EHCI_QH_NUM          CONFIG_USBHOST_PIPE_NUM
-#define CONFIG_USB_EHCI_QTD_NUM         3
-#define CONFIG_USB_EHCI_ITD_NUM         20
+#define CONFIG_USB_EHCI_QTD_NUM         (CONFIG_USB_EHCI_QH_NUM * 3)
+#define CONFIG_USB_EHCI_ITD_NUM         4
 #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
 // #define CONFIG_USB_EHCI_CONFIGFLAG
 // #define CONFIG_USB_EHCI_ISO
 // #define CONFIG_USB_EHCI_WITH_OHCI
+// #define CONFIG_USB_EHCI_DESC_DCACHE_ENABLE
 
 /* ---------------- OHCI Configuration ---------------- */
 #define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
+#define CONFIG_USB_OHCI_ED_NUM CONFIG_USBHOST_PIPE_NUM
+#define CONFIG_USB_OHCI_TD_NUM 3
+// #define CONFIG_USB_OHCI_DESC_DCACHE_ENABLE
 
 /* ---------------- XHCI Configuration ---------------- */
 #define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
@@ -268,9 +329,17 @@
  * (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
  * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
  */
-// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4)
+// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
 
 /* ---------------- MUSB Configuration ---------------- */
 // #define CONFIG_USB_MUSB_SUNXI
 
+#ifndef usb_phyaddr2ramaddr
+#define usb_phyaddr2ramaddr(addr) (addr)
+#endif
+
+#ifndef usb_ramaddr2phyaddr
+#define usb_ramaddr2phyaddr(addr) (addr)
+#endif
+
 #endif

bsp/hpmicro/hpm6750evk2/board/Kconfig

@@ -361,25 +361,19 @@ menu "On-chip Peripheral Drivers"
        default n
        if BSP_USING_USB
             config BSP_USING_USB_DEVICE
-                bool "Enable USB Device, default is msc ramdisk"
+                bool "Enable USB Device"
                 default n
                 select RT_USING_CHERRYUSB
                 select RT_CHERRYUSB_DEVICE
                 select RT_CHERRYUSB_DEVICE_SPEED_HS
                 select RT_CHERRYUSB_DEVICE_HPM
-                select RT_CHERRYUSB_DEVICE_MSC
-                select RT_CHERRYUSB_DEVICE_TEMPLATE_MSC
             config BSP_USING_USB_HOST
                 bool "Enable USB Host"
                 default n
                 select RT_USING_CACHE
                 select RT_USING_CHERRYUSB
                 select RT_CHERRYUSB_HOST
                 select RT_CHERRYUSB_HOST_EHCI_HPM
-                select RT_CHERRYUSB_HOST_CDC_ACM
-                select RT_CHERRYUSB_HOST_HID
-                select RT_CHERRYUSB_HOST_MSC
-                select RT_CHERRYUSB_HOST_CDC_RNDIS
        endif
 
 

bsp/hpmicro/hpm6750evk2/board/usb_config.h

@@ -20,14 +20,23 @@
 /* Enable print with color */
 #define CONFIG_USB_PRINTF_COLOR_ENABLE
 
-/* data align size when use dma */
-#ifndef CONFIG_USB_ALIGN_SIZE
+#define CONFIG_USB_DCACHE_ENABLE
+
+/* data align size when use dma or use dcache */
+#ifdef CONFIG_USB_DCACHE_ENABLE
+#define CONFIG_USB_ALIGN_SIZE HPM_L1C_CACHELINE_SIZE // 32 or 64
+#else
 #define CONFIG_USB_ALIGN_SIZE 4
 #endif
 
 /* attribute data into no cache ram */
 #define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable")))
 
+/* use usb_memcpy default for high performance but cost more flash memory.
+ * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4.
+*/
+// #define CONFIG_USB_MEMCPY_DISABLE
+
 /* ================= USB Device Stack Configuration ================ */
 
 /* Ep0 in and out transfer buffer */
@@ -49,6 +58,20 @@
 /* Enable test mode */
 // #define CONFIG_USBDEV_TEST_MODE
 
+/* enable advance desc register api */
+#define CONFIG_USBDEV_ADVANCE_DESC
+
+/* move ep0 setup handler from isr to thread */
+// #define CONFIG_USBDEV_EP0_THREAD
+
+#ifndef CONFIG_USBDEV_EP0_PRIO
+#define CONFIG_USBDEV_EP0_PRIO 4
+#endif
+
+#ifndef CONFIG_USBDEV_EP0_STACKSIZE
+#define CONFIG_USBDEV_EP0_STACKSIZE 2048
+#endif
+
 #ifndef CONFIG_USBDEV_MSC_MAX_LUN
 #define CONFIG_USBDEV_MSC_MAX_LUN 1
 #endif
@@ -83,6 +106,28 @@
 #define CONFIG_USBDEV_MSC_STACKSIZE 2048
 #endif
 
+#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE
+#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS
+#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME
+#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256
+#endif
+
+#define CONFIG_USBDEV_MTP_THREAD
+
+#ifndef CONFIG_USBDEV_MTP_PRIO
+#define CONFIG_USBDEV_MTP_PRIO 4
+#endif
+
+#ifndef CONFIG_USBDEV_MTP_STACKSIZE
+#define CONFIG_USBDEV_MTP_STACKSIZE 4096
+#endif
+
 #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE
 #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156
 #endif
@@ -101,6 +146,7 @@
 #endif
 
 #define CONFIG_USBDEV_RNDIS_USING_LWIP
+#define CONFIG_USBDEV_CDC_ECM_USING_LWIP
 
 /* ================ USB HOST Stack Configuration ================== */
 
@@ -211,6 +257,11 @@
 #define CONFIG_USBDEV_EP_NUM USB_SOC_DCD_MAX_ENDPOINT_COUNT
 #endif
 
+// #define CONFIG_USBDEV_SOF_ENABLE
+
+/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. */
+#define CONFIG_USB_HS
+
 /* ---------------- FSDEV Configuration ---------------- */
 //#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference
 
@@ -221,7 +272,7 @@
 // #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
 /* IN Endpoints Max packet Size / 4 */
 // #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
-// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
+// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4)
 // #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
 // #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
 // #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
@@ -230,6 +281,8 @@
 // #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
 // #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
 
+// #define CONFIG_USB_DWC2_DMA_ENABLE
+
 /* ---------------- MUSB Configuration ---------------- */
 // #define CONFIG_USB_MUSB_SUNXI
 
@@ -247,15 +300,19 @@
 #define CONFIG_USB_EHCI_HCCR_OFFSET     (0x100)
 #define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024
 #define CONFIG_USB_EHCI_QH_NUM          CONFIG_USBHOST_PIPE_NUM
-#define CONFIG_USB_EHCI_QTD_NUM         3
-#define CONFIG_USB_EHCI_ITD_NUM         20
+#define CONFIG_USB_EHCI_QTD_NUM         (CONFIG_USB_EHCI_QH_NUM * 3)
+#define CONFIG_USB_EHCI_ITD_NUM         4
 // #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE
 // #define CONFIG_USB_EHCI_CONFIGFLAG
 // #define CONFIG_USB_EHCI_ISO
 // #define CONFIG_USB_EHCI_WITH_OHCI
+// #define CONFIG_USB_EHCI_DESC_DCACHE_ENABLE
 
 /* ---------------- OHCI Configuration ---------------- */
 #define CONFIG_USB_OHCI_HCOR_OFFSET (0x0)
+#define CONFIG_USB_OHCI_ED_NUM CONFIG_USBHOST_PIPE_NUM
+#define CONFIG_USB_OHCI_TD_NUM 3
+// #define CONFIG_USB_OHCI_DESC_DCACHE_ENABLE
 
 /* ---------------- XHCI Configuration ---------------- */
 #define CONFIG_USB_XHCI_HCCR_OFFSET (0x0)
@@ -269,11 +326,19 @@
  * (largest USB packet used / 4) + 1 for status information + 1 transfer complete +
  * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario
  */
-// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4)
+// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE))
 
 /* ---------------- MUSB Configuration ---------------- */
 // #define CONFIG_USB_MUSB_SUNXI
 
-#define CONFIG_USB_EHCI_HPMICRO         (1)
+#ifndef usb_phyaddr2ramaddr
+#define usb_phyaddr2ramaddr(addr) (addr)
+#endif
+
+#ifndef usb_ramaddr2phyaddr
+#define usb_ramaddr2phyaddr(addr) (addr)
+#endif
+
+#define CONFIG_USB_EHCI_HPMICRO 1
 
 #endif