Bluegene Interrupt Controller (BIC)

Overview

• Each core of PPC450 defines 16 interrupt vectors (6 asynchronous, 10 synchronous)
• External interrupts are routed to one of three vectors: External Input, Critical Input, Machine Check.
• When an (non-masked) interrupt occurs, execution begins at the 16 byte aligned address given by a 16 bits the Interrupt Vector Prefix Register (IVPR) and 12 bits from the corresponding Interrupt Vector Offset Register (IVOR)
• No explicit way to synthesize an interrupt in PPC450. They can, however, be emulated in software with relatively few instructions.
• IPIs behave just like other external interrupt sources but can only be asserted by software.

Bluegene Interrupt Controller (BIC)

• External interrupts are assigned specific inputs on the interrupt controller (BIC).
• An external interrupt can be routed to one-or-all cores, causing one of the three asynchronous interrupt vectors to fire on those cores.
• A software interrupt handler must query the BIC to determine which device caused the interrupt.

Interrupt Vectors

• PPC450 defines 16 interrupt vectors. There are no user defined vectors.
• Most of the vectors are defined for synchronous interrupts. There are three for asynchronous interrupts. These are Machine Check, Critical Input and External Input. There are also three vectors for asynchronous time-related interrupts.
• Asynchronous interrupts are prioritized in the order above. They can pre-empt depending on the setting of a per-core register.

IPIs

• Software can cause any interrupt to be asserted by setting the corresponding bit in the BIC. IPIs are therefore only IRQs not connected to any device.
• In Bluegene/P there are 32 IRQs available for the use of IPI

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The BIC

• Contains three 32-bit sources registers per core: critical, non-critical, machine check.
• Each bit corresponds to a request group (0-31)
• Each group contains up to 32 "interrupt status elements" per-group.

Receive

• When core receives an interrupt from the BIC, we read the corresponding hierarchy register (Critical, Non-Critical, or Machine Check) to determine which group caused the interrupt. The specific interrupt is set in the group's source register. Enable
• To enable/register an interrupt on the BIC, we must write to the appropriate 4bit field in the corresponding groups target selection register.
• The target selection register is a 128bit block (or, four 32bit int) partitioned into thirty two 4bit IRQ registers.
• Each IRQ register is given a 4bit value to specify the behaviour of that interrupt.
  0000: Disabled
  0001-0011: Broadcast (Non-Crit, Crit, MC)
  0100-0111: Non-Critical (Core 0,1,2,3)
  1000-1011: Critical (Core 0,1,2,3)
  1100-1111: Machine Check (Core 0,1,2,3)

Groups

• A group consists of:
  • one 32-bit interrupt status register
  • four target select registers
  • four interrupt control registers (status, rd_clr_status, status_clr, status_set)
  • 12 masked IRQ registers
• Each bit in a groups interrupt status register is determined interrupt request from a device
• Status bits are level-sensitive to device interrupts, i.e., it captures and holds a signal from the device.
• Therefore, the device signal can set, but not unset, an interrupt status bit.
• In order to clear the status bit, it is necessary to first clear the device IRQ.
• Interrupt status register is controlled by the interrupt control registers.

Target Select Register

• Each group has a corresponding 128bit block partitioned into 4 32bit target registers (one per core)
• Each of the 32bits correspond to the 32 interrupts within that group.

Masked IRQ Registers

• As there is a single Interrupt Status Register in a group, it is not possible for a core to determine which of the sources in the group generated an interrupt.
• There are 12 auxiliary registers, named Masked IRQ Registers, mapping the IRQ source to each interrupt type (non-critical, critical and machine-check) and core.

Routing

• Any interrupt request source can be router to one-or-all core or no cores (equivalent to disabling that interrupt).
• When receiving an interrupt request, the Status bit is set and stays set until it is explicitly reset by accessing the Interrupt Control Register.