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gds.yaml
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test: change default testbench license to Apache-2.0 gds #14: Commit b906f3d pushed by urish
May 30, 2024 14:14 37s main
main
May 30, 2024 14:14 37s
suppress warning for unused inputs gds #13: Commit 2c112d6 pushed by urish
May 27, 2024 12:33 47s main
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May 27, 2024 12:33 47s
docs: twitter account link gds #12: Commit 7a4440c pushed by urish
May 12, 2024 20:01 39s main
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May 12, 2024 20:01 39s
ci(fpga): experimental FPGA bitstream action gds #11: Commit 67f5971 pushed by urish
May 2, 2024 08:41 28s main
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May 2, 2024 08:41 28s
ci(fpga): experimental FPGA bitstream action gds #10: Commit 33f31df pushed by urish
May 2, 2024 08:41 30s main
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May 2, 2024 08:41 30s
Update README.md gds #9: Commit 6229636 pushed by mattvenn
April 28, 2024 18:25 30s main
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April 28, 2024 18:25 30s
docs: explain the "ena" pin better gds #8: Commit 4bc03dd pushed by urish
April 22, 2024 06:47 34s main
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April 22, 2024 06:47 34s
docs: link to explain about custom clock config gds #7: Commit da3fd6a pushed by urish
April 20, 2024 19:43 29s main
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April 20, 2024 19:43 29s
fix: disable "MAGIC_DEF_LABELS" in config.tcl gds #6: Commit 3bb2b5b pushed by urish
April 20, 2024 19:39 48s main
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April 20, 2024 19:39 48s
Update README.md gds #5: Commit 53c0d23 pushed by mattvenn
April 19, 2024 18:05 47s main
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April 19, 2024 18:05 47s
TT07 Verilog Project Template gds #4: Commit 3d8eb83 pushed by urish
April 19, 2024 17:56 31s main
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April 19, 2024 17:56 31s
TT07 Verilog Project Template gds #3: Commit 08d98e2 pushed by urish
April 19, 2024 17:48 26s main
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April 19, 2024 17:48 26s
TT07 Verilog Project Template gds #2: Commit 1528e05 pushed by urish
April 19, 2024 17:47 30s main
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April 19, 2024 17:47 30s
TT07 Verilog Project Template gds #1: Commit 46172fb pushed by urish
April 19, 2024 17:45 1m 4s main
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April 19, 2024 17:45 1m 4s