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Add $macc_v2
#4818
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Add $macc_v2
#4818
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This use case is better served with having an extra port of plain summands, and leave So that you have
where each Cc @phsauter also @widlarizer @whitequark (we touched on |
Rebased |
This reminded me that cell help construction needs documenting. Still WIP but here's a link to the docs preview build. While not necessary, it would certainly make me happy for new cells being added to use the v2 style and give things titles, since at some point I would like to update everything in simlib.v to use it. |
Sure, let me review that and update |
What's the value in retaining plain summands (C port)? Is that for matching some kind of techmappable primitive? |
As opposed to connecting the summands to the A/B ports, or not fusing the addition into the |
Initially I was thinking as opposed to not holding those inside |
It can be more efficient to combine the operations as they can share the reduction tree.
See the comment above, it's meant to make writing "techmap" rules less awkward |
So, what do we want to techmap them to? For example, the existence of the redundant B port in |
E.g. the ELAU implementation of a multiply-add: https://github.com/pulp-platform/ELAU/blob/master/src/AddMulSgn.sv
I don't know of anyone writing Verilog rules matching on the |
Ah, so all |
That should be already the case. With this PR Yosys stops emitting any |
What are the reasons/motivation for this change?
$macc
is needlessly complex: theCONFIG
parameter uses a convoluted encoding, and it has a redundantB
port for single-bit summands.With
$macc_v2
the goal is to make it simpler, so much so that it's not unreasonable to write techmap rules matching on this cell in plain Verilog (as opposed to just deferring tomaccmap
).Explain how this is achieved.
Changes done in v2 (edited):
$mem_v2
, which encodes a dynamic number of read/write ports in a similar manner)Based off #4817, which can go in first to make this one easier to review.TODO:
$macc_v2
techmap.v