rename: add -move-to-cell option in -wire mode

[jix]

What are the reasons/motivation for this change?

For some use cases it is desirable to transfer names from wires to their driving cells.

Explain how this is achieved.

This adds a -move-to-cell option to rename -wire which doesn't add a suffix to the cell name but instead adds a suffix to the wire name, if necessary to avoid conflicts.

It also makes rename -wire use the correct HDL indices for wires with non-zero-indexing, whether using -move-to-cell or not.

If applicable, please suggest to reviewers how they can test the change.

By replacing rename -wire with rename -wire -move-to-cell in an existing flow.

[jix]

@tspyrou @precisionmoon: This implements the renaming we were discussing. To make it easy to test this change in isolation, I rebased this PR branch on top of the Yosys commit that the ORFS master is currently using. Note that this adds a new rename variant, so testing it does require also changing rename -wire to rename -wire -move-to-cell in ORFS's synth.tcl.

[widlarizer]

This is a pattern that I created with rename -hide that prevents the new mode from doing its job as it checks whatever is the directly driven wire without traversing the tree of aliases or querying a sigmap that would have a public name promoted. The purpose for this pass is to be able to refer cells post-synthesis, so I think we can assume such a shape won't happen, but I'm not 100% sure

[widlarizer]

On some level, I would expect printing to respect the uptoness of the original hdl objects, so I don't think we should be undoing it here with the swap

In case it's useful / becomes part of a test, here's the input for trying out this code path

read_verilog <<EOF
module top(input [0:7] a, input [0:7] b, output [0:4] o1, output [4:0] o2);
    wire [0:7] int1 = a + b;
    wire [0:7] int2 = a + b;
    assign o1[0:3] = int1[0:3];
    assign o2[3:0] = int2[4:7];
endmodule
EOF

proc -noopt
rename -hide w:int*
opt
rename -wire -move-to-cell