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ad9081: vck190: Added support for JESD204B
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ad9209: vck190: Changed serial connections and added reset signals
Signed-off-by: Bogdan Luncan <[email protected]>
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@bluncan
bluncan committed Jul 17, 2024
1 parent 9ca41b7 commit 1bc51d8
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Showing 15 changed files with 1,400 additions and 390 deletions.
3 changes: 2 additions & 1 deletion library/jesd204/jesd204_versal_gt_adapter_rx/Makefile
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####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := jesd204_versal_gt_adapter_rx

GENERIC_DEPS += jesd204_versal_gt_adapter_rx.v
GENERIC_DEPS += lane_align.v

XILINX_DEPS += ../jesd204_common/sync_header_align.v
XILINX_DEPS += jesd204_versal_gt_adapter_rx_ip.tcl
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123 changes: 85 additions & 38 deletions library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
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@@ -1,73 +1,120 @@
// ***************************************************************************
// ***************************************************************************
<<<<<<< HEAD
// Copyright (C) 2017, 2018, 2020-2022, 2024 Analog Devices, Inc. All rights reserved.
=======
// Copyright (C) 2017, 2018, 2020-2024 Analog Devices, Inc. All rights reserved.
>>>>>>> cbd399e80 (ad9081: vck190: Added support for JESD204B)
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module jesd204_versal_gt_adapter_rx (
module jesd204_versal_gt_adapter_rx #(
parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
) (
// Interface to Physical Layer
input [127 : 0] rxdata,
input [5 : 0] rxheader,
input [ 5 : 0] rxheader,
input [ 15 : 0] rxctrl0,
input [ 15 : 0] rxctrl1,
input [ 7 : 0] rxctrl2,
input [ 7 : 0] rxctrl3,
output rxgearboxslip,
input [1 : 0] rxheadervalid,
input [ 1 : 0] rxheadervalid,
output rxslide,

// Interface to Link layer core
output [63:0] rx_data,
output [1:0] rx_header,
output rx_block_sync,
output [ 63 : 0] rx_data,
output [ 3 : 0] rx_charisk,
output [ 3 : 0] rx_disperr,
output [ 3 : 0] rx_notintable,
output [ 1 : 0] rx_header,
output rx_block_sync,
input en_char_align,

input usr_clk
input resetn,
input usr_clk
);

wire rxgearboxslip_s;
reg [63:0] rxdata_d;
reg [ 1:0] rxheader_d;
reg rxgearboxslip_d;
reg [ 1:0] rxheadervalid_d;
reg [15:0] rxctrl0_d;
reg [15:0] rxctrl1_d;
reg [ 7:0] rxctrl3_d;

always @(posedge usr_clk) begin
rxdata_d <= rxdata[63:0];
rxheader_d <= rxheader[1:0];
rxgearboxslip_d <= rxgearboxslip_s;
rxctrl0_d <= rxctrl0;
rxctrl1_d <= rxctrl1;
rxctrl3_d <= rxctrl3;
end

// Sync header alignment
wire rx_bitslip_req_s;
reg [5:0] rx_bitslip_done_cnt = 'h0;
always @(posedge usr_clk) begin
if (rx_bitslip_done_cnt[5]) begin
rx_bitslip_done_cnt <= 'b0;
end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin
rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
generate if (LINK_MODE == 2) begin
// Sync header alignment
wire rx_bitslip_req_s;
reg [5:0] rx_bitslip_done_cnt = 'h0;
always @(posedge usr_clk) begin
if (rx_bitslip_done_cnt[5]) begin
rx_bitslip_done_cnt <= 'b0;
end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin
rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
end
end
end

reg rx_bitslip_req_s_d = 1'b0;
always @(posedge usr_clk) begin
rx_bitslip_req_s_d <= rx_bitslip_req_s;
end
reg rx_bitslip_req_s_d = 1'b0;
always @(posedge usr_clk) begin
rx_bitslip_req_s_d <= rx_bitslip_req_s;
end

assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
assign rxgearboxslip = rxgearboxslip_d;
assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
assign rxgearboxslip = rxgearboxslip_d;

wire [63:0] rxdata_flip;
genvar i;
for (i = 0; i < 64; i=i+1) begin
assign rxdata_flip[63-i] = rxdata_d[i];
end
wire [63:0] rxdata_flip;
genvar i;
for (i = 0; i < 64; i=i+1) begin
assign rxdata_flip[63-i] = rxdata_d[i];
end

// Sync header alignment
sync_header_align i_sync_header_align (
.clk(usr_clk),
.reset(~rxheadervalid[0]),
// Flip header bits and data
.i_data({rxheader_d[0],rxheader_d[1],rxdata_flip[63:0]}),
.i_slip(rx_bitslip_req_s),
.i_slip_done(rx_bitslip_done_cnt[5]),
.o_data(rx_data),
.o_header(rx_header),
.o_block_sync(rx_block_sync));

assign rx_disperr = 4'b0;
assign rx_charisk = 4'b0;
assign rx_notintable = 4'b0;
assign rxslide = 1'b0;
end else begin
assign rx_data = {32'b0, rxdata_d[31:0]};
assign rx_header = rxheader_d[1:0];

// Sync header alignment
sync_header_align i_sync_header_align (
.clk(usr_clk),
.reset(~rxheadervalid[0]),
// Flip header bits and data
.i_data({rxheader_d[0],rxheader_d[1],rxdata_flip[63:0]}),
.i_slip(rx_bitslip_req_s),
.i_slip_done(rx_bitslip_done_cnt[5]),
.o_data(rx_data),
.o_header(rx_header),
.o_block_sync(rx_block_sync));
assign rx_charisk = rxctrl0_d[3:0];
assign rx_disperr = rxctrl1_d[3:0];
assign rx_notintable = rxctrl3_d[3:0];
assign rx_block_sync = 1'b0;
assign rxgearboxslip = 1'b0;

lane_align i_lane_align (
.usr_clk (usr_clk),
.resetn (resetn),
.rxdata (rxdata[31:0]),
.rx_slide (rxslide),
.en_char_align (en_char_align));
end
endgenerate

endmodule
11 changes: 10 additions & 1 deletion library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################

Expand All @@ -9,6 +9,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create jesd204_versal_gt_adapter_rx
adi_ip_files jesd204_versal_gt_adapter_rx [list \
jesd204_versal_gt_adapter_rx.v \
lane_align.v \
../jesd204_common/sync_header_align.v \
]

Expand All @@ -23,6 +24,9 @@ adi_add_bus "RX" "master" \
{ \
{ "rx_data" "rxdata" } \
{ "rx_header" "rxheader" } \
{ "rx_charisk" "rxcharisk"} \
{ "rx_disperr" "rxdisperr"} \
{ "rx_notintable" "rxnotintable"} \
{ "rx_block_sync" "rxblock_sync" } \
}

Expand All @@ -32,6 +36,11 @@ adi_add_bus "RX_GT_IP_Interface" "master" \
{ \
{ "rxdata" "ch_rxdata" } \
{ "rxheader" "ch_rxheader" } \
{ "rxctrl0" "ch_rxctrl0" } \
{ "rxctrl1" "ch_rxctrl1" } \
{ "rxctrl2" "ch_rxctrl2" } \
{ "rxctrl3" "ch_rxctrl3" } \
{ "rxslide" "ch_rxslide" } \
{ "rxheadervalid" "ch_rxheadervalid" } \
{ "rxgearboxslip" "ch_rxgearboxslip" } \
}
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81 changes: 81 additions & 0 deletions library/jesd204/jesd204_versal_gt_adapter_rx/lane_align.v
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@@ -0,0 +1,81 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************

module lane_align (
input usr_clk,
input resetn,
input [31:0] rxdata,
input en_char_align,
output rx_slide
);

localparam K_CHARACTER = 32'hBCBCBCBC;

localparam WAIT_FOR_CHAR_ALIGN = 0;
localparam CHECK_ALIGNMENT = 1;
localparam PULSE_SLIDE = 2;
localparam WAIT_DELAY = 3;

reg [2:0] state;
reg [2:0] next_state;
reg [5:0] counter;
reg [5:0] next_counter;
wire rx_slide_s;

always @(negedge resetn or posedge usr_clk) begin
if (!resetn) begin
state <= WAIT_FOR_CHAR_ALIGN;
counter <= 'd0;
end else begin
state <= next_state;
counter <= next_counter;
end
end

always @(*) begin
next_counter <= counter;
case (state)
WAIT_FOR_CHAR_ALIGN: begin
if (en_char_align) begin
next_state <= CHECK_ALIGNMENT;
end else begin
next_state <= WAIT_FOR_CHAR_ALIGN;
end
end
CHECK_ALIGNMENT: begin
if (rxdata == K_CHARACTER) begin
next_state <= WAIT_FOR_CHAR_ALIGN;
end else begin
next_counter <= 'd0;
next_state <= PULSE_SLIDE;
end
end
PULSE_SLIDE: begin // a pulse is valid only if it takes 2 usr_clk cycles
if (counter == 'd1) begin
next_state <= WAIT_DELAY;
next_counter <= 'd0;
end else begin
next_state <= PULSE_SLIDE;
next_counter <= counter + 1'b1;
end
end
WAIT_DELAY: begin // wait 32 usr_clk cycles between each pulse
if (counter[5]) begin
next_state <= CHECK_ALIGNMENT;
end else begin
next_state <= WAIT_DELAY;
next_counter <= counter + 1'b1;
end
end
endcase
end

assign rx_slide_s = (state == PULSE_SLIDE)? 1'b1 : 1'b0;

assign rx_slide = rx_slide_s;

endmodule
2 changes: 1 addition & 1 deletion library/jesd204/jesd204_versal_gt_adapter_tx/Makefile
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@@ -1,5 +1,5 @@
####################################################################################
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
## Copyright (c) 2018 - 2024 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
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58 changes: 44 additions & 14 deletions library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
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@@ -1,33 +1,63 @@
// ***************************************************************************
// ***************************************************************************
<<<<<<< HEAD
// Copyright (C) 2017-2019, 2021, 2024 Analog Devices, Inc. All rights reserved.
=======
// Copyright (C) 2017-2019, 2021-2024 Analog Devices, Inc. All rights reserved.
>>>>>>> cbd399e80 (ad9081: vck190: Added support for JESD204B)
// SPDX short identifier: ADIJESD204
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module jesd204_versal_gt_adapter_tx (
output reg [127 : 0] txdata,
output reg [5 : 0] txheader,

module jesd204_versal_gt_adapter_tx #(
parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
) (
output [127 : 0] txdata,
output [ 5 : 0] txheader,
output [ 15 : 0] txctrl0,
output [ 15 : 0] txctrl1,
output [ 7 : 0] txctrl2,
// Interface to Link layer core
input [63:0] tx_data,
input [1:0] tx_header,
input [ 63 : 0] tx_data,
input [ 1 : 0] tx_header,
input [ 3 : 0] tx_charisk,

input usr_clk
);

wire [63:0] tx_data_flip;
genvar i;
for (i = 0; i < 64; i=i+1) begin
assign tx_data_flip[63-i] = tx_data[i];
end
wire [63:0] txdata_d;
wire [ 5:0] txheader_d;
wire [ 7:0] txctrl2_d;

// Flip header bits and data
always @(posedge usr_clk) begin
txdata <= {64'b0, tx_data_flip};
txheader <= {4'b0, tx_header[0], tx_header[1]};
txdata_d <= tx_data;
txheader_d <= tx_header;
txctrl2_d <= {4'b0, tx_charisk};
end

generate if (LINK_MODE == 2) begin
wire [63:0] tx_data_flip;
genvar i;
for (i = 0; i < 64; i=i+1) begin
assign tx_data_flip[63-i] = txdata_d[i];
end

// Flip header bits and data
assign txdata <= {64'b0, tx_data_flip};
assign txheader <= {4'b0, txheader_d[0], txheader_d[1]};

assign txctrl0 = 16'b0;
assign txctrl1 = 16'b0;
assign txctrl2 = 16'b0;
end else begin
assign txdata = {96'b0, txdata_d[31:0]};
assign txheader = {4'b0, txheader_d};
assign txctrl0 = 16'b0;
assign txctrl1 = 16'b0;
assign txctrl2 = txctrl2_d;
end
endgenerate

endmodule
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