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DMA Generic Transfer Start Synchronization #1341
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The resulting cpack2->dma connection is weird, because you renamed on the DMAC side but not on CPACK, only popped of the intf.
I would rename it from packed_fifo_wr_sync
to packed_sync
on cpack, and on the tcl files
to:
ad_connect <inst>_pack/packed_sync <inst>_dma/sync
instead of:
ad_connect <inst>_pack/packed_fifo_wr_sync <inst>_dma/sync
I synthesized pulsar_adc/coraz7s and cn0540/de10nano with the PR rebased to main without issues.
I also rebased #1332 onto yours and I got only a few merge conflicts that I was able to easily resolve.
the suggested tb also works rebased to main
From the CI run, can you ensure these projects were already failing?
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V2:
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V2.1: Updated the Optimization Mode on fmcomms8.a10soc in order to improve timing; rebased on the latest changes on main. |
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Great work!
I believe we could squash into a single commit when merging since the intermediary commits are non-functional, just make sure to update the message body to properly describe the changes.
This commit adds a generic 'sync' port used for transfer start. The signal used for synchronization is assumed to be synchronous with the interface clock. On the receive AXI Streaming interface, the user can choose to receive the synchronization signal on TUSER instead of 'sync', which is the default setting, configurable through the AXIS_TUSER_SYNC synthesis parameter. Signed-off-by: Ionut Podgoreanu <[email protected]>
Signed-off-by: Ionut Podgoreanu <[email protected]>
Signed-off-by: Ionut Podgoreanu <[email protected]>
Signed-off-by: Ionut Podgoreanu <[email protected]>
Signed-off-by: Ionut Podgoreanu <[email protected]>
Signed-off-by: Ionut Podgoreanu <[email protected]>
V2.2: Some minor edits to improve the build results; also rebased on the latest changes on main.
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PR Description
This PR adds a generic sync port used for transfer start synchronization. The signal used for synchronization is assumed to be synchronous with the interface clock which needs to be triggered by the sync signal.
On the receive AXI Streaming interface, the user can choose to receive the synchronization signal on TUSER instead of 'sync',
which is the default setting, configurable through the AXIS_TUSER_SYNC synthesis parameter.
The fifo_wr interface has the SYNC signal removed, since it is now a generic synchronization port, applicable to all interfaces. Therefore, all affected IPs and Projects had to be updated to address this change.
Tested this change in simulation. Please refer to: https://github.com/analogdevicesinc/testbenches/tree/pluto_phaser_tx_sync
PR Type
PR Checklist