Development for the AD35xxR #1472
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It is supporting dual SPI for the ad3542r Signed-off-by: <[email protected]>
It is supporting Single SPI (Classic), Dual SPI, and Quad SPI mode on the same bitstream. Changed the regmap, the reg DAC_CUSTOM_CTRL needs to assert the MULTI_IO_MODE field to choose the SPI mode. Increased the frequency of the sclk from 16.5Mhz to 66Mhz. Changed the AD3552r documentation to show the architecture changes. Signed-off-by: <[email protected]>
some changes on the doc of the AD3552r Signed-off-by: <[email protected]>
Signed-off-by: <[email protected]>
some changes on the doc of the AD3552r Signed-off-by: <[email protected]>
Changed some parts of the documentation. Inserted EVAL-AD3552R documentation with some more info Signed-off-by: <[email protected]>
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The axi_ad35xx AXI Stream input interface is not defined |
Removed axi libraries because they were substitute by axi_ad35xxr Removed evaluation board projects because they were substituted by ad35xxr_evb Signed-off-by: <[email protected]>
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PR Description
Developed a single IP for the AD3552R, AD3551R, AD3542R, and AD3541R parts.
This new IP has support for Single SPI (Classic), Dual SPI, and Quad SPI. It supports
changing the SPI mode during execution by setting the multi_io_mode field.
It was tested the interface file with some modifications on the tb.
Created a documentation for this new IP, and the regmap modification on the axi_ad35xxr.
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