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ad9081_fmca_ebz: common: versal_transceiver: Force progdiv_clk to float #1505

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@bluncan bluncan commented Nov 5, 2024

PR Description

The [rx/tx]_progdiv_clock was truncated if the lane rate was an integer. So for a lane rate of '10', the ref clock calculated was 151.000 instead of 151.515.

PR Type

  • Bug fix (change that fixes an issue)
  • New feature (change that adds new functionality)
  • Breaking change (has dependencies in other repos or will cause CI to fail)

PR Checklist

  • I have followed the code style guidelines
  • I have performed a self-review of changes
  • I have compiled all hdl projects and libraries affected by this PR
  • I have tested in hardware affected projects, at least on relevant boards
  • I have commented my code, at least hard-to-understand parts
  • I have signed off all commits from this PR
  • I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
  • I have not introduced new Warnings/Critical Warnings on compilation
  • I have added new hdl testbenches or updated existing ones

The [rx/tx]_progdiv_clock was truncated if the lane rate was an integer.
So for a lane rate of '10', the ref clock calculated was 151.000
instead of 151.515.

Signed-off-by: Bogdan Luncan <[email protected]>
@bluncan bluncan force-pushed the versal_fix_progdiv_clk_for_integer_lanerate branch from 3da0453 to 337a379 Compare November 5, 2024 05:48
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@gastmaier gastmaier left a comment

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Tested the behavior with

set var2 [format %.3f [expr 2 * 1000.0 / 3]]
666.667
set var2 [format %.3f [expr 2 * 1000 / 3]]
666.000

at vivado tcl console

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3 participants