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ad9081_fmca_ebz: common: versal_transceiver: Force progdiv_clk to float #1505

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ad9081_fmca_ebz: common: versal_transceiver: Force progdiv_clk to float #1505

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4 changes: 2 additions & 2 deletions projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -215,8 +215,8 @@ proc create_versal_phy {
puts "intf_cfg: ${intf_cfg}"
puts "assymmetric_mode: ${asymmetric_mode}"

set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / ${clk_divider}]]
set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / ${clk_divider}]]
set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000.0 / ${clk_divider}]]
set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000.0 / ${clk_divider}]]
set preset ${transceiver}-JESD204_64B66B

if {$intf_cfg == "RX"} {
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