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unit_level_tb: Revert SV support #1509

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unit_level_tb: Revert SV support #1509

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Commits on Nov 7, 2024

  1. unit_level_tb: Revert SV support 

    - Added SystemVerilog support breaks some of the current unit level testbenches

Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
    @IstvanZsSzekely
    IstvanZsSzekely committed Nov 7, 2024
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