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Dev dds 32b phase #864

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merged 4 commits into from
Sep 26, 2023
Merged

Dev dds 32b phase #864

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9f76c31
DAC DDS: Add support for DDS phase width > 16
AndreiGrozav Feb 1, 2022
1638573
ad_ip_jesd204_tpl_dac: Increase DDS phase DW support
AndreiGrozav Feb 1, 2022
fef6173
ad9361: Add support for config DDS phase resolution
AndreiGrozav Mar 24, 2022
0a7aa21
up_dac_channel: Cosmetic additions
AndreiGrozav May 16, 2023
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2 changes: 2 additions & 0 deletions library/axi_ad9361/axi_ad9361.v
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Expand Up @@ -60,6 +60,7 @@ module axi_ad9361 #(
parameter DAC_DATAPATH_DISABLE = 0,
parameter DAC_DDS_DISABLE = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_PHASE_DW = 16,
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter DAC_USERPORTS_DISABLE = 0,
Expand Down Expand Up @@ -671,6 +672,7 @@ module axi_ad9361 #(
.PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE),
.INIT_DELAY (DAC_INIT_DELAY),
.DAC_DDS_DISABLE (DAC_DDS_DISABLE_INT),
.DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
Expand Down
5 changes: 5 additions & 0 deletions library/axi_ad9361/axi_ad9361_tx.v
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Expand Up @@ -51,6 +51,7 @@ module axi_ad9361_tx #(
parameter INIT_DELAY = 0,
parameter DAC_DDS_DISABLE = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_PHASE_DW = 16,
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter USERPORTS_DISABLE = 0,
Expand Down Expand Up @@ -226,6 +227,7 @@ module axi_ad9361_tx #(
.DISABLE (0),
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
Expand Down Expand Up @@ -261,6 +263,7 @@ module axi_ad9361_tx #(
.DISABLE (0),
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
Expand Down Expand Up @@ -296,6 +299,7 @@ module axi_ad9361_tx #(
.DISABLE (MODE_1R1T),
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
Expand Down Expand Up @@ -331,6 +335,7 @@ module axi_ad9361_tx #(
.DISABLE (MODE_1R1T),
.DAC_DDS_DISABLE (DAC_DDS_DISABLE),
.DAC_DDS_TYPE (DAC_DDS_TYPE),
.DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW),
.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
Expand Down
12 changes: 7 additions & 5 deletions library/axi_ad9361/axi_ad9361_tx_channel.v
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Expand Up @@ -44,6 +44,7 @@ module axi_ad9361_tx_channel #(
parameter DISABLE = 0,
parameter DAC_DDS_DISABLE = 0,
parameter DAC_DDS_TYPE = 1,
parameter DAC_DDS_PHASE_DW = 16,
parameter DAC_DDS_CORDIC_DW = 14,
parameter DAC_DDS_CORDIC_PHASE_DW = 13,
parameter USERPORTS_DISABLE = 0,
Expand Down Expand Up @@ -105,11 +106,11 @@ module axi_ad9361_tx_channel #(
wire [15:0] dac_iqcor_data_s;
wire [11:0] dac_dds_data_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [DAC_DDS_PHASE_DW-1:0] dac_dds_init_1_s;
wire [DAC_DDS_PHASE_DW-1:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [DAC_DDS_PHASE_DW-1:0] dac_dds_init_2_s;
wire [DAC_DDS_PHASE_DW-1:0] dac_dds_incr_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
Expand Down Expand Up @@ -321,7 +322,7 @@ module axi_ad9361_tx_channel #(
ad_dds #(
.DISABLE (DAC_DDS_DISABLE),
.DDS_DW (12),
.PHASE_DW (16),
.PHASE_DW (DAC_DDS_PHASE_DW),
.DDS_TYPE (DAC_DDS_TYPE),
.CORDIC_DW (DAC_DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
Expand Down Expand Up @@ -349,6 +350,7 @@ module axi_ad9361_tx_channel #(
.COMMON_ID (6'h11),
.CHANNEL_ID (CHANNEL_ID),
.DDS_DISABLE (DAC_DDS_DISABLE),
.DDS_PHASE_DW (DAC_DDS_PHASE_DW),
.USERPORTS_DISABLE (USERPORTS_DISABLE),
.IQCORRECTION_DISABLE (IQCORRECTION_DISABLE)
) i_up_dac_channel (
Expand Down
6 changes: 3 additions & 3 deletions library/common/ad_dds.v
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Expand Up @@ -41,7 +41,7 @@ module ad_dds #(
parameter DISABLE = 0,
// range 8-24
parameter DDS_DW = 16,
// range 8-16 (FIX ME)
// range 8-32
parameter PHASE_DW = 16,
// set 1 for CORDIC or 2 for Polynomial
parameter DDS_TYPE = 1,
Expand All @@ -62,8 +62,8 @@ module ad_dds #(
input dac_valid,
input [ 15:0] tone_1_scale,
input [ 15:0] tone_2_scale,
input [ 15:0] tone_1_init_offset,
input [ 15:0] tone_2_init_offset,
input [ PHASE_DW-1:0] tone_1_init_offset,
input [ PHASE_DW-1:0] tone_2_init_offset,
input [ PHASE_DW-1:0] tone_1_freq_word,
input [ PHASE_DW-1:0] tone_2_freq_word,
output reg [DDS_DW*CLK_RATIO-1:0] dac_dds_data
Expand Down
110 changes: 83 additions & 27 deletions library/common/up_dac_channel.v
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Expand Up @@ -43,6 +43,7 @@ module up_dac_channel #(
parameter CHANNEL_ID = 4'h0,
parameter CHANNEL_NUMBER = 8'b0,
parameter DDS_DISABLE = 0,
parameter DDS_PHASE_DW = 16,
parameter USERPORTS_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 0,
parameter XBAR_ENABLE = 0
Expand All @@ -53,11 +54,11 @@ module up_dac_channel #(
input dac_clk,
input dac_rst,
output [15:0] dac_dds_scale_1,
output [15:0] dac_dds_init_1,
output [15:0] dac_dds_incr_1,
output [15:0] dac_dds_scale_2,
output [15:0] dac_dds_init_2,
output [15:0] dac_dds_incr_2,
output [DDS_PHASE_DW-1:0] dac_dds_init_1,
output [DDS_PHASE_DW-1:0] dac_dds_incr_1,
output [DDS_PHASE_DW-1:0] dac_dds_init_2,
output [DDS_PHASE_DW-1:0] dac_dds_incr_2,
output [15:0] dac_pat_data_1,
output [15:0] dac_pat_data_2,
output [ 3:0] dac_data_sel,
Expand Down Expand Up @@ -108,6 +109,10 @@ module up_dac_channel #(
reg [15:0] up_dac_dds_scale_2 = 'd0;
reg [15:0] up_dac_dds_init_2 = 'd0;
reg [15:0] up_dac_dds_incr_2 = 'd0;
reg [15:0] up_dac_dds_init_1_extend = 'd0;
reg [15:0] up_dac_dds_incr_1_extend = 'd0;
reg [15:0] up_dac_dds_init_2_extend = 'd0;
reg [15:0] up_dac_dds_incr_2_extend = 'd0;
reg [15:0] up_dac_pat_data_2 = 'd0;
reg [15:0] up_dac_pat_data_1 = 'd0;
reg up_dac_iqcor_enb = 'd0;
Expand Down Expand Up @@ -136,8 +141,18 @@ module up_dac_channel #(

// internal signals

wire up_wreq_s;
wire up_rreq_s;
wire up_wreq_s;
wire up_rreq_s;
wire [ 5:0] dds_phase_w = DDS_PHASE_DW[5:0];

wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_dds_init_1_extend;
wire [15:0] dac_dds_incr_1_extend;
wire [15:0] dac_dds_init_2_extend;
wire [15:0] dac_dds_incr_2_extend;

// 2's complement function

Expand Down Expand Up @@ -180,6 +195,10 @@ module up_dac_channel #(
up_dac_dds_scale_2 <= 'd0;
up_dac_dds_init_2 <= 'd0;
up_dac_dds_incr_2 <= 'd0;
up_dac_dds_init_1_extend <= 'd0;
up_dac_dds_incr_1_extend <= 'd0;
up_dac_dds_init_2_extend <= 'd0;
up_dac_dds_incr_2_extend <= 'd0;
end
end else begin
always @(negedge up_rstn or posedge up_clk) begin
Expand All @@ -190,6 +209,10 @@ module up_dac_channel #(
up_dac_dds_scale_2 <= 'd0;
up_dac_dds_init_2 <= 'd0;
up_dac_dds_incr_2 <= 'd0;
up_dac_dds_init_1_extend <= 'd0;
up_dac_dds_incr_1_extend <= 'd0;
up_dac_dds_init_2_extend <= 'd0;
up_dac_dds_incr_2_extend <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin
up_dac_dds_scale_1 <= up_wdata[15:0];
Expand All @@ -205,6 +228,14 @@ module up_dac_channel #(
up_dac_dds_init_2 <= up_wdata[31:16];
up_dac_dds_incr_2 <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hb)) begin
up_dac_dds_init_1_extend <= up_wdata[31:16];
up_dac_dds_incr_1_extend <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hc)) begin
up_dac_dds_init_2_extend <= up_wdata[31:16];
up_dac_dds_incr_2_extend <= up_wdata[15:0];
end
end
end
end
Expand Down Expand Up @@ -350,7 +381,7 @@ module up_dac_channel #(
up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[3:0])
4'h0: up_rdata_int <= { 16'd0, up_dac_dds_scale_1};
4'h0: up_rdata_int <= { 10'd0, dds_phase_w, up_dac_dds_scale_1};
4'h1: up_rdata_int <= { up_dac_dds_init_1, up_dac_dds_incr_1};
4'h2: up_rdata_int <= { 16'd0, up_dac_dds_scale_2};
4'h3: up_rdata_int <= { up_dac_dds_init_2, up_dac_dds_incr_2};
Expand All @@ -363,6 +394,8 @@ module up_dac_channel #(
dac_usr_datatype_bits};
4'h9: up_rdata_int <= { dac_usr_interpolation_m, dac_usr_interpolation_n};
4'ha: up_rdata_int <= { 30'd0, up_dac_iq_mode};
4'hb: up_rdata_int <= { up_dac_dds_init_1_extend, up_dac_dds_incr_1_extend};
4'hc: up_rdata_int <= { up_dac_dds_init_2_extend, up_dac_dds_incr_2_extend};
default: up_rdata_int <= 0;
endcase
end else begin
Expand Down Expand Up @@ -404,25 +437,29 @@ module up_dac_channel #(
// dac control & status

up_xfer_cntrl #(
.DATA_WIDTH(177)
.DATA_WIDTH(240)
) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_dac_iq_mode,
up_dac_iqcor_enb,
up_dac_iqcor_coeff_tc_1,
up_dac_iqcor_coeff_tc_2,
up_dac_dds_scale_tc_1,
up_dac_dds_init_1,
up_dac_dds_incr_1,
up_dac_dds_scale_tc_2,
up_dac_dds_init_2,
up_dac_dds_incr_2,
up_dac_pat_data_1,
up_dac_pat_data_2,
up_dac_data_sel_m,
up_dac_mask_enable,
up_dac_src_chan_sel}),
.up_data_cntrl ({ up_dac_iq_mode, // 2
up_dac_iqcor_enb, // 1
up_dac_iqcor_coeff_tc_1, // 16
up_dac_iqcor_coeff_tc_2, // 16
up_dac_dds_scale_tc_1, // 16
up_dac_dds_init_1, // 16
up_dac_dds_incr_1, // 16
up_dac_dds_scale_tc_2, // 16
up_dac_dds_init_2, // 16
up_dac_dds_incr_2, // 16
up_dac_dds_init_1_extend, // 16
up_dac_dds_incr_1_extend, // 16
up_dac_dds_init_2_extend, // 16
up_dac_dds_incr_2_extend, // 16
up_dac_pat_data_1, // 16
up_dac_pat_data_2, // 16
up_dac_data_sel_m, // 4
up_dac_mask_enable, // 1
up_dac_src_chan_sel}), // 8
.up_xfer_done (),
.d_rst (dac_rst),
.d_clk (dac_clk),
Expand All @@ -431,15 +468,34 @@ module up_dac_channel #(
dac_iqcor_coeff_1,
dac_iqcor_coeff_2,
dac_dds_scale_1,
dac_dds_init_1,
dac_dds_incr_1,
dac_dds_init_1_s,
dac_dds_incr_1_s,
dac_dds_scale_2,
dac_dds_init_2,
dac_dds_incr_2,
dac_dds_init_2_s,
dac_dds_incr_2_s,
dac_dds_init_1_extend,
dac_dds_incr_1_extend,
dac_dds_init_2_extend,
dac_dds_incr_2_extend,
dac_pat_data_1,
dac_pat_data_2,
dac_data_sel,
dac_mask_enable,
dac_src_chan_sel}));

generate
if (DDS_PHASE_DW > 16) begin
localparam DDS_EXT_DW = DDS_PHASE_DW - 16 - 1;
assign dac_dds_init_1 = {dac_dds_init_1_extend[DDS_EXT_DW:0], dac_dds_init_1_s};
assign dac_dds_incr_1 = {dac_dds_incr_1_extend[DDS_EXT_DW:0], dac_dds_incr_1_s};
assign dac_dds_init_2 = {dac_dds_init_2_extend[DDS_EXT_DW:0], dac_dds_init_2_s};
assign dac_dds_incr_2 = {dac_dds_incr_2_extend[DDS_EXT_DW:0], dac_dds_incr_2_s};
end else begin
assign dac_dds_init_1 = dac_dds_init_1_s[DDS_PHASE_DW-1:0];
assign dac_dds_incr_1 = dac_dds_incr_1_s[DDS_PHASE_DW-1:0];
assign dac_dds_init_2 = dac_dds_init_2_s[DDS_PHASE_DW-1:0];
assign dac_dds_incr_2 = dac_dds_incr_2_s[DDS_PHASE_DW-1:0];
end
endgenerate

endmodule
2 changes: 1 addition & 1 deletion library/common/up_dac_common.v
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Expand Up @@ -118,7 +118,7 @@ module up_dac_common #(

// parameters

localparam VERSION = 32'h00090162;
localparam VERSION = 32'h00090262;

// internal registers

Expand Down
13 changes: 8 additions & 5 deletions library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
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Expand Up @@ -52,6 +52,7 @@ module ad_ip_jesd204_tpl_dac #(
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DDS_PHASE_DW = 16,
parameter DATAPATH_DISABLE = 0,
parameter IQCORRECTION_DISABLE = 1,
parameter EXT_SYNC = 0,
Expand Down Expand Up @@ -125,11 +126,11 @@ module ad_ip_jesd204_tpl_dac #(
wire dac_dds_format;

wire [NUM_CHANNELS*16-1:0] dac_dds_scale_0_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_init_0_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_incr_0_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_scale_1_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_init_1_s;
wire [NUM_CHANNELS*16-1:0] dac_dds_incr_1_s;
wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0_s;
wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0_s;
wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1_s;
wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1_s;
wire [NUM_CHANNELS*16-1:0] dac_pat_data_0_s;
wire [NUM_CHANNELS*16-1:0] dac_pat_data_1_s;
wire [NUM_CHANNELS*4-1:0] dac_data_sel_s;
Expand All @@ -156,7 +157,8 @@ module ad_ip_jesd204_tpl_dac #(
.DATA_PATH_WIDTH (DATA_PATH_WIDTH),
.PADDING_TO_MSB_LSB_N (PADDING_TO_MSB_LSB_N),
.NUM_PROFILES(1),
.EXT_SYNC (EXT_SYNC)
.EXT_SYNC (EXT_SYNC),
.DDS_PHASE_DW (DDS_PHASE_DW)
) i_regmap (
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
Expand Down Expand Up @@ -234,6 +236,7 @@ module ad_ip_jesd204_tpl_dac #(
.DDS_TYPE (DDS_TYPE),
.DDS_CORDIC_DW (DDS_CORDIC_DW),
.DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
.DDS_PHASE_DW (DDS_PHASE_DW),
.EXT_SYNC (EXT_SYNC)
) i_core (
.clk (link_clk),
Expand Down
11 changes: 6 additions & 5 deletions library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
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Expand Up @@ -44,6 +44,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
parameter DDS_TYPE = 1,
parameter DDS_CORDIC_DW = 16,
parameter DDS_CORDIC_PHASE_DW = 16,
parameter DDS_PHASE_DW = 16,
parameter Q_OR_I_N = 0
) (

Expand All @@ -68,11 +69,11 @@ module ad_ip_jesd204_tpl_dac_channel #(
input dac_mask_enable,

input [15:0] dac_dds_scale_0,
input [15:0] dac_dds_init_0,
input [15:0] dac_dds_incr_0,
input [15:0] dac_dds_scale_1,
input [15:0] dac_dds_init_1,
input [15:0] dac_dds_incr_1,
input [DDS_PHASE_DW-1:0] dac_dds_init_0,
input [DDS_PHASE_DW-1:0] dac_dds_incr_0,
input [DDS_PHASE_DW-1:0] dac_dds_init_1,
input [DDS_PHASE_DW-1:0] dac_dds_incr_1,

input [15:0] dac_pat_data_0,
input [15:0] dac_pat_data_1,
Expand Down Expand Up @@ -159,7 +160,7 @@ module ad_ip_jesd204_tpl_dac_channel #(
ad_dds #(
.DISABLE (DATAPATH_DISABLE),
.DDS_DW (CONVERTER_RESOLUTION),
.PHASE_DW (16),
.PHASE_DW (DDS_PHASE_DW),
.DDS_TYPE (DDS_TYPE),
.CORDIC_DW (DDS_CORDIC_DW),
.CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW),
Expand Down
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