Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

test_harness_system_bd: Fix axi_cpu_interconnect bug for MI >= 16 #47

Closed
wants to merge 1 commit into from

Conversation

FilipG24
Copy link
Contributor

@FilipG24 FilipG24 commented Sep 28, 2023

In test_harness block design, axi_mem_interconnect is connected to axi_cpu_interconnect but in case axi_cpu_interconnect has more than 16 interfaces connected, a smartconnect error will occur: "ERROR: [xilinx.com:ip:smartconnect:1.0-1] test_harness_axi_cpu_interconnect_0: For SmartConnect test_harness_axi_cpu_interconnect_0, the use of >16 MI is reserved for low-bandwidth pathways only. Either the SI must be AXI4LITE or all MI must be 32-bit-wide AXI4LITE. Otherwise, you may cascade multiple instances with <=16 MI".
So in order to solve this another smartconnect is used to separate the axi_mem_interconnect from the axi_cpu_interconnect!
This was tested only for the adrv9009 Testbench!

@podgori
Copy link
Contributor

podgori commented Nov 8, 2023

I believe that this issue would be better addressed if the axi_cpu_interconnect implemented as a SmartConnect instance is configured to use only AXI4LITE interfaces. This is because mng_axi_vip which connects to the axi_cpu_interconnect as a master interface only uses AXI4LITE read/write transfers.

The SmartConnect 16 MI limitation which is encountered during the current simulation run can be relaxed to 64 MI AXI4LITE according to the documentation:

  • Up to 16 Slave Interfaces (SI) and up to 16 Master Interfaces (MI) per instance.

    • Supports connecting one SI to up to 64 AXI4-Lite MI.

However, this will have to be further investigated, since after some experiments in which I set all MIs to AXI4LITE, an error is received:
INFO: [xilinx.com:ip:smartconnect:1.0-1] test_harness_axi_cpu_interconnect_0: SmartConnect test_harness_axi_cpu_interconnect_0 is in Low-Area Mode.
ERROR: [IP_Flow 19-3458] Validation failed for parameter 'NUM_MI(NUM_MI)' for BD Cell 'axi_cpu_interconnect/inst/ar_la_out_swbd'. Value '17' is out of the range (1,16)

So, in the meantime, until this issue is solved. I suggest fetching the latest changes on the main branch and using AXI Interconnects through the following setting:
set use_smartconnect 0

@IstvanZsSzekely IstvanZsSzekely marked this pull request as draft February 2, 2024 07:31
@IstvanZsSzekely
Copy link
Contributor

Closing this PR as another PR has been opened to solve the issue of cascading interconnects.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

3 participants