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SystemVerilog Design Project created April 2016 - May 2016 at UIUC

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tetris-sysverilog

Design Project created April 2016 - May 2016 at UIUC. This is the full implementation of the game of Tetris, which we ran on the Altera Cyclone IV FPGA using Quartus II.

Project Partner: Patrick Su

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SystemVerilog Design Project created April 2016 - May 2016 at UIUC

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