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[WIP] Wishbone config #1

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[WIP] Wishbone config #1

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75dc726
Use Wishbone for control and CSR frontend
kabrodzki Apr 27, 2020
b7bc387
Use WishboneClassic reader and writer frontends
kabrodzki Apr 27, 2020
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16 changes: 8 additions & 8 deletions src/main/scala/DMAController/DMATop.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -32,18 +32,18 @@ import chisel3.util.Queue

class DMATop extends Module{
val io = IO(new Bundle{
val control = Flipped(new AXI4Lite(DMATop.controlAddrWidth, DMATop.controlDataWidth))
val read = Flipped(new AXIStream(DMATop.readDataWidth))
val write = new AXI4(DMATop.addrWidth, DMATop.writeDataWidth)
val control = new WishboneSlave(DMATop.controlAddrWidth, DMATop.controlDataWidth)
val read = new WishboneMaster(DMATop.addrWidth, DMATop.readDataWidth)
val write = new WishboneMaster(DMATop.addrWidth, DMATop.writeDataWidth)
val irq = new InterruptBundle
val sync = new SyncBundle
})

val csrFrontend = Module(new AXI4LiteCSR(DMATop.addrWidth))
val csrFrontend = Module(new WishboneCSR(DMATop.addrWidth))

val readerFrontend = Module(new AXIStreamSlave(DMATop.addrWidth, DMATop.readDataWidth))
val readerFrontend = Module(new WishboneClassicReader(DMATop.addrWidth, DMATop.readDataWidth))

val writerFrontend = Module(new AXI4Writer(DMATop.addrWidth, DMATop.writeDataWidth))
val writerFrontend = Module(new WishboneClassicWriter(DMATop.addrWidth, DMATop.writeDataWidth))

val csr = Module(new CSR(DMATop.addrWidth))

Expand Down Expand Up @@ -74,9 +74,9 @@ object DMATop {
val readDataWidth = 32
val writeDataWidth = 32
val readMaxBurst = 0
val writeMaxBurst = 256
val writeMaxBurst = 0
val reader4KBarrier = false
val writer4KBarrier = true
val writer4KBarrier = false

val controlDataWidth = 32
val controlAddrWidth = 32
Expand Down