Port to chisel 6

antmicro · May 16, 2024 · 038df8b · 038df8b
1 parent b5fc53c
commit 038df8b
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Showing 40 changed files with 132 additions and 174 deletions.
diff --git a/.gitignore b/.gitignore
@@ -340,8 +340,9 @@ hs_err_pid*
 
 # chisel output
 *.v
+*.sv
 *.fir
 *.anno.json
 
 *.rgba
-out.png
+out*.png
diff --git a/build.sbt b/build.sbt
@@ -1,17 +1,5 @@
 // See README.md for license details.
 
-def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
-  Seq() ++ {
-    // If we're building with Scala > 2.11, enable the compile option
-    //  switch to support our anonymous Bundle definitions:
-    //  https://github.com/scala/bug/issues/10047
-    CrossVersion.partialVersion(scalaVersion) match {
-      case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
-      case _ => Seq("-Xsource:2.11")
-    }
-  }
-}
-
 def javacOptionsVersion(scalaVersion: String): Seq[String] = {
   Seq() ++ {
     // Scala 2.12 requires Java 8. We continue to generate
@@ -28,30 +16,34 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
 
 name := "chisel-dma"
 
-version := "3.5.3"
+version := "6.0.0"
 
-scalaVersion := "2.12.13"
-
-crossScalaVersions := Seq("2.11.12", "2.12.13")
+scalaVersion := "2.13.12"
 
 resolvers ++= Seq(
   Resolver.sonatypeRepo("snapshots"),
   Resolver.sonatypeRepo("releases")
 )
-// Chisel 3.5
-addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.3" cross CrossVersion.full)
+resolvers -= DefaultMavenRepository
+resolvers += "Maven Repo" at "https://mvnrepository.com/artifacts"
+
+// Chisel 6.0.0
+addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full)
 
 // Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
 val defaultVersions = Map(
-  "chisel3" -> "3.5.+",
-  "chiseltest" -> "0.5.0",
-  "chisel-iotesters" -> "2.5.5+"
-  )
-libraryDependencies ++= Seq("chisel3","chiseltest","chisel-iotesters").map {
-  dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }
+  "chisel" -> "6.0.0",
+  "chiseltest" -> "6.0-SNAPSHOT"
+)
+
+val defaultOrgs = Map(
+  "chisel" -> "org.chipsalliance",
+  "chiseltest" -> "edu.berkeley.cs"
+)
 
-libraryDependencies += "com.typesafe.play" %% "play-json" % "2.8.+"
+libraryDependencies ++= Seq("chisel","chiseltest").map {
+  dep: String => defaultOrgs(dep) %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }
 
-scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
+libraryDependencies += "com.typesafe.play" %% "play-json" % "2.10.5"
 
-javacOptions ++= javacOptionsVersion(scalaVersion.value)
+javacOptions ++= javacOptionsVersion(scalaVersion.value)
diff --git a/src/main/scala/DMAController/Bus/WishboneMaster.scala b/src/main/scala/DMAController/Bus/WishboneMaster.scala
@@ -15,7 +15,7 @@ SPDX-License-Identifier: Apache-2.0
 package DMAController.Bus
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.log2Ceil
 
 class WishboneMaster(val addrWidth : Int, val dataWidth : Int) extends Bundle{
   /* data */

diff --git a/src/main/scala/DMAController/Bus/WishboneSlave.scala b/src/main/scala/DMAController/Bus/WishboneSlave.scala
@@ -15,7 +15,7 @@ SPDX-License-Identifier: Apache-2.0
 package DMAController.Bus
 
 import chisel3._
-import chisel3.util._
+import chisel3.util.log2Ceil
 
 class WishboneSlave(val addrWidth : Int, val dataWidth : Int) extends Bundle{
   /* data */

diff --git a/src/main/scala/DMAController/CSR/ClearCSR.scala b/src/main/scala/DMAController/CSR/ClearCSR.scala
@@ -13,9 +13,9 @@ SPDX-License-Identifier: Apache-2.0
 */
 
 package DMAController.CSR
-import DMAController.DMADriver
-import DMAUtils.DMAModule
+
 import chisel3._
+import DMAUtils.DMAModule
 import DMAController.DMAConfig.DMAConfig
 
 class ClearCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) {

diff --git a/src/main/scala/DMAController/CSR/SetCSR.scala b/src/main/scala/DMAController/CSR/SetCSR.scala
@@ -16,7 +16,6 @@ package DMAController.CSR
 
 import chisel3._
 import DMAUtils.DMAModule
-import DMAController.DMADriver
 import DMAController.DMAConfig._
 
 class SetCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) {

diff --git a/src/main/scala/DMAController/CSR/SimpleCSR.scala b/src/main/scala/DMAController/CSR/SimpleCSR.scala
@@ -16,7 +16,6 @@ package DMAController.CSR
 
 import chisel3._
 import DMAUtils.DMAModule
-import DMAController.DMADriver
 import DMAController.DMAConfig._
 
 class SimpleCSR(config: DMAConfig) extends DMAModule(config) {

diff --git a/src/main/scala/DMAController/CSR/StatusCSR.scala b/src/main/scala/DMAController/CSR/StatusCSR.scala
@@ -14,9 +14,8 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.CSR
 
-import DMAUtils.DMAModule
-import DMAController.DMADriver
 import chisel3._
+import DMAUtils.DMAModule
 import DMAController.DMAConfig._
 
 class StatusCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig){

diff --git a/src/main/scala/DMAController/DMAConfig.scala b/src/main/scala/DMAController/DMAConfig.scala
@@ -15,11 +15,6 @@ SPDX-License-Identifier: Apache-2.0
 package DMAController.DMAConfig
 
 import chisel3._
-import DMAController.Bus._
-import DMAController.CSR.CSR
-import DMAController.Frontend._
-import DMAController.Worker.{InterruptBundle, WorkerCSRWrapper, SyncBundle}
-import chisel3.util.Queue
 
 class DMAConfig(
     val busConfig: String = "AXI_AXIL_AXI",

diff --git a/src/main/scala/DMAController/DMADriver.scala b/src/main/scala/DMAController/DMADriver.scala
@@ -14,10 +14,9 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController
 
-import chisel3.stage.ChiselStage
+import circt.stage.ChiselStage
 import DMAConfig._
 import DMAUtils.{DMAParseInput, DMALogger}
-import DMAController.DMAConfig._
 
 object DMADriver extends App {
   val config =
@@ -36,5 +35,5 @@ object DMADriver extends App {
       }
     }
 
-  (new ChiselStage).emitVerilog(new DMATop(config))
+  ChiselStage.emitSystemVerilogFile(new DMATop(config))
 }
diff --git a/src/main/scala/DMAController/DMATop.scala b/src/main/scala/DMAController/DMATop.scala
@@ -15,8 +15,6 @@ SPDX-License-Identifier: Apache-2.0
 package DMAController
 
 import chisel3._
-import chisel3.util._
-import DMAController.Bus._
 import DMAController.CSR._
 import DMAController.Frontend._
 import DMAController.Worker.{InterruptBundle, WorkerCSRWrapper, SyncBundle}

diff --git a/src/main/scala/DMAController/Frontend/AXI4LiteCSR.scala b/src/main/scala/DMAController/Frontend/AXI4LiteCSR.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus.AXI4Lite
-import DMAController.CSR.{CSR, CSRBusBundle}
-import DMAController.Worker.{WorkerCSRWrapper}
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.Bus.AXI4Lite
+import DMAController.CSR.CSRBusBundle
+import DMAController.DMAConfig.DMAConfig
 
 class AXI4LiteCSR(addrWidth: Int, dataWidth: Int, regCount: Int,
     dmaConfig: DMAConfig) extends CSRBus[AXI4Lite](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/AXI4LiteWriter.scala b/src/main/scala/DMAController/Frontend/AXI4LiteWriter.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus._
-import DMAController.Worker.{WorkerCSRWrapper, XferDescBundle}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.Bus._
+import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 class AXI4LiteWriter(val addrWidth: Int, val dataWidth: Int,
   dmaConfig: DMAConfig) extends IOBus[AXI4Lite](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/AXI4Reader.scala b/src/main/scala/DMAController/Frontend/AXI4Reader.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus._
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
+import DMAController.Bus._
 import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 class AXI4Reader(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig)
     extends IOBus[AXI4](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/AXI4Writer.scala b/src/main/scala/DMAController/Frontend/AXI4Writer.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus._
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.Bus._
+import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 class AXI4Writer(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig)
     extends IOBus[AXI4](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/AXIStreamMaster.scala b/src/main/scala/DMAController/Frontend/AXIStreamMaster.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus.AXIStream
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.Bus.AXIStream
+import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 class AXIStreamMaster(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig)
     extends IOBus[AXIStream](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/AXIStreamSlave.scala b/src/main/scala/DMAController/Frontend/AXIStreamSlave.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus.AXIStream
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.Bus.AXIStream
+import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 class AXIStreamSlave(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig)
     extends IOBus[AXIStream](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/BusBase.scala b/src/main/scala/DMAController/Frontend/BusBase.scala
@@ -13,14 +13,14 @@ SPDX-License-Identifier: Apache-2.0
 */
 
 package DMAController.Frontend
-import DMAController.Bus._
-import DMAController.CSR.{CSR, CSRBusBundle}
-import DMAController.Worker.{WorkerCSRWrapper, XferDescBundle}
-import DMAUtils.DMAModule
+
 import chisel3._
 import chisel3.util._
-import DMAController.DMADriver
-import DMAController.DMAConfig._
+import DMAUtils.DMAModule
+import DMAController.Bus._
+import DMAController.CSR.CSRBusBundle
+import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 abstract class IOBus[+T](config: DMAConfig) extends DMAModule(config) {
   val io : Bundle {

diff --git a/src/main/scala/DMAController/Frontend/WishboneCSR.scala b/src/main/scala/DMAController/Frontend/WishboneCSR.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus.WishboneSlave
-import DMAController.CSR.{CSR, CSRBusBundle}
-import DMAController.Worker.WorkerCSRWrapper
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.CSR.CSRBusBundle
+import DMAController.Bus.WishboneSlave
+import DMAController.DMAConfig.DMAConfig
 
 class WishboneCSR(addrWidth: Int, dataWidth: Int, regCount: Int,
     dmaConfig: DMAConfig) extends CSRBus[WishboneSlave](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedReader.scala b/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedReader.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus.WishboneMaster
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
 import DMAController.DMAConfig._
+import DMAController.Bus.WishboneMaster
+import DMAController.Worker.XferDescBundle
 
 class WishboneClassicPipelinedReader(val addrWidth: Int, val dataWidth: Int,
     config: DMAConfig) extends IOBus[WishboneMaster](config) {

diff --git a/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedWriter.scala b/src/main/scala/DMAController/Frontend/WishboneClassicPipelinedWriter.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus.WishboneMaster
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.Bus.WishboneMaster
+import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 class WishboneClassicPipelinedWriter(val addrWidth: Int, val dataWidth: Int,
     dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/WishboneClassicReader.scala b/src/main/scala/DMAController/Frontend/WishboneClassicReader.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus.WishboneMaster
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.Bus.WishboneMaster
+import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 class WishboneClassicReader(val addrWidth: Int, val dataWidth: Int,
     dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) {

diff --git a/src/main/scala/DMAController/Frontend/WishboneClassicWriter.scala b/src/main/scala/DMAController/Frontend/WishboneClassicWriter.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Frontend
 
-import DMAController.Bus.WishboneMaster
-import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
-import DMAController.CSR.CSR
 import chisel3._
 import chisel3.util._
-import DMAController.DMAConfig._
+import DMAController.Bus.WishboneMaster
+import DMAController.DMAConfig.DMAConfig
+import DMAController.Worker.XferDescBundle
 
 class WishboneClassicWriter(val addrWidth: Int, val dataWidth: Int,
     dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) {

diff --git a/src/main/scala/DMAController/Worker/AddressGenerator.scala b/src/main/scala/DMAController/Worker/AddressGenerator.scala
@@ -17,8 +17,7 @@ package DMAController.Worker
 import chisel3._
 import chisel3.util._
 import DMAUtils.DMAModule
-import DMAController.DMAConfig._
-import DMAController.DMATop
+import DMAController.DMAConfig.DMAConfig
 
 class AddressGenerator(val addrWidth: Int, val dataWidth: Int,
     dmaConfig: DMAConfig) extends DMAModule(dmaConfig) {

diff --git a/src/main/scala/DMAController/Worker/InterruptController.scala b/src/main/scala/DMAController/Worker/InterruptController.scala
@@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0
 
 package DMAController.Worker
 
-import DMAController.CSR.{CSRRegBundle, SetCSR, SimpleCSR}
 import chisel3._
 import chisel3.util.Cat
 import DMAUtils.DMAModule
-import DMAController.DMADriver
-import DMAController.DMAConfig._
+import DMAController.CSR._
+import DMAController.DMAConfig.DMAConfig
 
 class InterruptController(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) {
   val io = IO(new Bundle {