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Porting the fastvdma to Chisel 6 (sbt version) #24

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Porting the fastvdma to Chisel 6 (sbt version) #24

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038df8b
Port to chisel 6
pznikola May 16, 2024
d225720
Install Verilator
pznikola May 16, 2024
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1 change: 1 addition & 0 deletions .github/workflows/build.yml
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Expand Up @@ -14,4 +14,5 @@ jobs:
echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add
sudo apt update && sudo apt install -y sbt
sudo apt-get update -y && sudo apt-get install -y verilator
make testall
3 changes: 2 additions & 1 deletion .gitignore
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Expand Up @@ -340,8 +340,9 @@ hs_err_pid*

# chisel output
*.v
*.sv
*.fir
*.anno.json

*.rgba
out.png
out*.png
46 changes: 19 additions & 27 deletions build.sbt
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@@ -1,17 +1,5 @@
// See README.md for license details.

def scalacOptionsVersion(scalaVersion: String): Seq[String] = {
Seq() ++ {
// If we're building with Scala > 2.11, enable the compile option
// switch to support our anonymous Bundle definitions:
// https://github.com/scala/bug/issues/10047
CrossVersion.partialVersion(scalaVersion) match {
case Some((2, scalaMajor: Long)) if scalaMajor < 12 => Seq()
case _ => Seq("-Xsource:2.11")
}
}
}

def javacOptionsVersion(scalaVersion: String): Seq[String] = {
Seq() ++ {
// Scala 2.12 requires Java 8. We continue to generate
Expand All @@ -28,30 +16,34 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {

name := "chisel-dma"

version := "3.5.3"
version := "6.0.0"

scalaVersion := "2.12.13"

crossScalaVersions := Seq("2.11.12", "2.12.13")
scalaVersion := "2.13.12"

resolvers ++= Seq(
Resolver.sonatypeRepo("snapshots"),
Resolver.sonatypeRepo("releases")
)
// Chisel 3.5
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.3" cross CrossVersion.full)
resolvers -= DefaultMavenRepository
resolvers += "Maven Repo" at "https://mvnrepository.com/artifacts"

// Chisel 6.0.0
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % "6.0.0" cross CrossVersion.full)

// Provide a managed dependency on X if -DXVersion="" is supplied on the command line.
val defaultVersions = Map(
"chisel3" -> "3.5.+",
"chiseltest" -> "0.5.0",
"chisel-iotesters" -> "2.5.5+"
)
libraryDependencies ++= Seq("chisel3","chiseltest","chisel-iotesters").map {
dep: String => "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }
"chisel" -> "6.0.0",
"chiseltest" -> "6.0-SNAPSHOT"
)

val defaultOrgs = Map(
"chisel" -> "org.chipsalliance",
"chiseltest" -> "edu.berkeley.cs"
)

libraryDependencies += "com.typesafe.play" %% "play-json" % "2.8.+"
libraryDependencies ++= Seq("chisel","chiseltest").map {
dep: String => defaultOrgs(dep) %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep)) }

scalacOptions ++= scalacOptionsVersion(scalaVersion.value)
libraryDependencies += "com.typesafe.play" %% "play-json" % "2.10.5"

javacOptions ++= javacOptionsVersion(scalaVersion.value)
javacOptions ++= javacOptionsVersion(scalaVersion.value)
2 changes: 1 addition & 1 deletion src/main/scala/DMAController/Bus/WishboneMaster.scala
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Expand Up @@ -15,7 +15,7 @@ SPDX-License-Identifier: Apache-2.0
package DMAController.Bus

import chisel3._
import chisel3.util._
import chisel3.util.log2Ceil

class WishboneMaster(val addrWidth : Int, val dataWidth : Int) extends Bundle{
/* data */
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2 changes: 1 addition & 1 deletion src/main/scala/DMAController/Bus/WishboneSlave.scala
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Expand Up @@ -15,7 +15,7 @@ SPDX-License-Identifier: Apache-2.0
package DMAController.Bus

import chisel3._
import chisel3.util._
import chisel3.util.log2Ceil

class WishboneSlave(val addrWidth : Int, val dataWidth : Int) extends Bundle{
/* data */
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4 changes: 2 additions & 2 deletions src/main/scala/DMAController/CSR/ClearCSR.scala
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Expand Up @@ -13,9 +13,9 @@ SPDX-License-Identifier: Apache-2.0
*/

package DMAController.CSR
import DMAController.DMADriver
import DMAUtils.DMAModule

import chisel3._
import DMAUtils.DMAModule
import DMAController.DMAConfig.DMAConfig

class ClearCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) {
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1 change: 0 additions & 1 deletion src/main/scala/DMAController/CSR/SetCSR.scala
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Expand Up @@ -16,7 +16,6 @@ package DMAController.CSR

import chisel3._
import DMAUtils.DMAModule
import DMAController.DMADriver
import DMAController.DMAConfig._

class SetCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig) {
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1 change: 0 additions & 1 deletion src/main/scala/DMAController/CSR/SimpleCSR.scala
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Expand Up @@ -16,7 +16,6 @@ package DMAController.CSR

import chisel3._
import DMAUtils.DMAModule
import DMAController.DMADriver
import DMAController.DMAConfig._

class SimpleCSR(config: DMAConfig) extends DMAModule(config) {
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3 changes: 1 addition & 2 deletions src/main/scala/DMAController/CSR/StatusCSR.scala
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Expand Up @@ -14,9 +14,8 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.CSR

import DMAUtils.DMAModule
import DMAController.DMADriver
import chisel3._
import DMAUtils.DMAModule
import DMAController.DMAConfig._

class StatusCSR(dmaConfig: DMAConfig) extends DMAModule(dmaConfig){
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5 changes: 0 additions & 5 deletions src/main/scala/DMAController/DMAConfig.scala
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Expand Up @@ -15,11 +15,6 @@ SPDX-License-Identifier: Apache-2.0
package DMAController.DMAConfig

import chisel3._
import DMAController.Bus._
import DMAController.CSR.CSR
import DMAController.Frontend._
import DMAController.Worker.{InterruptBundle, WorkerCSRWrapper, SyncBundle}
import chisel3.util.Queue

class DMAConfig(
val busConfig: String = "AXI_AXIL_AXI",
Expand Down
5 changes: 2 additions & 3 deletions src/main/scala/DMAController/DMADriver.scala
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Expand Up @@ -14,10 +14,9 @@ SPDX-License-Identifier: Apache-2.0

package DMAController

import chisel3.stage.ChiselStage
import circt.stage.ChiselStage
import DMAConfig._
import DMAUtils.{DMAParseInput, DMALogger}
import DMAController.DMAConfig._

object DMADriver extends App {
val config =
Expand All @@ -36,5 +35,5 @@ object DMADriver extends App {
}
}

(new ChiselStage).emitVerilog(new DMATop(config))
ChiselStage.emitSystemVerilogFile(new DMATop(config))
}
2 changes: 0 additions & 2 deletions src/main/scala/DMAController/DMATop.scala
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Expand Up @@ -15,8 +15,6 @@ SPDX-License-Identifier: Apache-2.0
package DMAController

import chisel3._
import chisel3.util._
import DMAController.Bus._
import DMAController.CSR._
import DMAController.Frontend._
import DMAController.Worker.{InterruptBundle, WorkerCSRWrapper, SyncBundle}
Expand Down
7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/AXI4LiteCSR.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus.AXI4Lite
import DMAController.CSR.{CSR, CSRBusBundle}
import DMAController.Worker.{WorkerCSRWrapper}
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus.AXI4Lite
import DMAController.CSR.CSRBusBundle
import DMAController.DMAConfig.DMAConfig

class AXI4LiteCSR(addrWidth: Int, dataWidth: Int, regCount: Int,
dmaConfig: DMAConfig) extends CSRBus[AXI4Lite](dmaConfig) {
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7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/AXI4LiteWriter.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus._
import DMAController.Worker.{WorkerCSRWrapper, XferDescBundle}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus._
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

class AXI4LiteWriter(val addrWidth: Int, val dataWidth: Int,
dmaConfig: DMAConfig) extends IOBus[AXI4Lite](dmaConfig) {
Expand Down
5 changes: 2 additions & 3 deletions src/main/scala/DMAController/Frontend/AXI4Reader.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus._
import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.Bus._
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

class AXI4Reader(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig)
extends IOBus[AXI4](dmaConfig) {
Expand Down
7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/AXI4Writer.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus._
import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus._
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

class AXI4Writer(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig)
extends IOBus[AXI4](dmaConfig) {
Expand Down
7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/AXIStreamMaster.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus.AXIStream
import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus.AXIStream
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

class AXIStreamMaster(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig)
extends IOBus[AXIStream](dmaConfig) {
Expand Down
7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/AXIStreamSlave.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus.AXIStream
import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus.AXIStream
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

class AXIStreamSlave(val addrWidth: Int, val dataWidth: Int, dmaConfig: DMAConfig)
extends IOBus[AXIStream](dmaConfig) {
Expand Down
12 changes: 6 additions & 6 deletions src/main/scala/DMAController/Frontend/BusBase.scala
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Expand Up @@ -13,14 +13,14 @@ SPDX-License-Identifier: Apache-2.0
*/

package DMAController.Frontend
import DMAController.Bus._
import DMAController.CSR.{CSR, CSRBusBundle}
import DMAController.Worker.{WorkerCSRWrapper, XferDescBundle}
import DMAUtils.DMAModule

import chisel3._
import chisel3.util._
import DMAController.DMADriver
import DMAController.DMAConfig._
import DMAUtils.DMAModule
import DMAController.Bus._
import DMAController.CSR.CSRBusBundle
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

abstract class IOBus[+T](config: DMAConfig) extends DMAModule(config) {
val io : Bundle {
Expand Down
7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/WishboneCSR.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus.WishboneSlave
import DMAController.CSR.{CSR, CSRBusBundle}
import DMAController.Worker.WorkerCSRWrapper
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.CSR.CSRBusBundle
import DMAController.Bus.WishboneSlave
import DMAController.DMAConfig.DMAConfig

class WishboneCSR(addrWidth: Int, dataWidth: Int, regCount: Int,
dmaConfig: DMAConfig) extends CSRBus[WishboneSlave](dmaConfig) {
Expand Down
5 changes: 2 additions & 3 deletions src/main/scala/DMAController/Frontend/WishboneClassicPipelinedReader.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus.WishboneMaster
import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus.WishboneMaster
import DMAController.Worker.XferDescBundle

class WishboneClassicPipelinedReader(val addrWidth: Int, val dataWidth: Int,
config: DMAConfig) extends IOBus[WishboneMaster](config) {
Expand Down
7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/WishboneClassicPipelinedWriter.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus.WishboneMaster
import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus.WishboneMaster
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

class WishboneClassicPipelinedWriter(val addrWidth: Int, val dataWidth: Int,
dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) {
Expand Down
7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/WishboneClassicReader.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus.WishboneMaster
import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus.WishboneMaster
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

class WishboneClassicReader(val addrWidth: Int, val dataWidth: Int,
dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) {
Expand Down
7 changes: 3 additions & 4 deletions src/main/scala/DMAController/Frontend/WishboneClassicWriter.scala
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Expand Up @@ -14,12 +14,11 @@ SPDX-License-Identifier: Apache-2.0

package DMAController.Frontend

import DMAController.Bus.WishboneMaster
import DMAController.Worker.{XferDescBundle, WorkerCSRWrapper}
import DMAController.CSR.CSR
import chisel3._
import chisel3.util._
import DMAController.DMAConfig._
import DMAController.Bus.WishboneMaster
import DMAController.DMAConfig.DMAConfig
import DMAController.Worker.XferDescBundle

class WishboneClassicWriter(val addrWidth: Int, val dataWidth: Int,
dmaConfig: DMAConfig) extends IOBus[WishboneMaster](dmaConfig) {
Expand Down
3 changes: 1 addition & 2 deletions src/main/scala/DMAController/Worker/AddressGenerator.scala
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Expand Up @@ -17,8 +17,7 @@ package DMAController.Worker
import chisel3._
import chisel3.util._
import DMAUtils.DMAModule
import DMAController.DMAConfig._
import DMAController.DMATop
import DMAController.DMAConfig.DMAConfig

class AddressGenerator(val addrWidth: Int, val dataWidth: Int,
dmaConfig: DMAConfig) extends DMAModule(dmaConfig) {
Expand Down
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